ADSP-21364SBBCZENG datasheet(33/52 Pages) AD

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ADSP-21364

Preliminary Technical Data

Rev. PrB

Page 33 of 52

September 2004

Parallel Data Acquisition Port (PDAP)

The timing requirements for the PDAP are provided in

Table 29. PDAP is the parallel mode operation of channel 0 of

the IDP. For details on the operation of the IDP, see the IDP

chapter of the ADSP-2136x SHARC Processor Hardware Refer-

ence. Note that the most significant 16 bits of external PDAP

data can be provided through either the parallel port AD15–0 or

the DAI_P20–5 pins. The remaining 4 bits can only be sourced

through DAI_P4–1. The timing below is valid at the

DAI_P20–1 pins or at the AD15–0 pins.

Table 29. Parallel Data Acquisition Port (PDAP)

Parameter

Min

Max

Unit

Timing Requirements

tSPCLKEN

PDAP_CLKEN Setup Before PDAP_CLK Sample Edge

2.5

tHPCLKEN

PDAP_CLKEN Hold After PDAP_CLK Sample Edge

2.5

tPDSD

PDAP_DAT Setup Before SCLK PDAP_CLK Sample Edge

2.5

tPDHD

PDAP_DAT Hold After SCLK PDAP_CLK Sample Edge

2.5

tPDCLKW

Clock Width

tPDCLK

Clock Period

Switching Characteristics

tPDHLDD

Delay of PDAP Strobe After Last PDAP_CLK Capture Edge for a Word

2 × tCCLK

tPDSTRB

PDAP Strobe Pulse Width

1 × tCCLK – 1

1 Source pins of DATA are ADDR7–0, DATA7–0, or DAI pins. Source pins for SCLK and FS are: 1) DAI pins, 2) CLKIN through PCG, or 3) DAI pins through PCG.

Figure 24. PDAP Timing

DAI_P20-1

(PDAP_CLK)

SAMPLE EDGE

tPDSD

tPDHD

tSPCLKEN

tHPCLKEN

tPDCLKW

DATA

DAI_P20-1

(PDAP_CLKEN)

tPDSTRB

tPDHLDD

DAI_P20-1

(PDAP_STROBE)

tPDCLK

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