ADSP-21364SBBCZENG datasheet(27/52 Pages) AD

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ADSP-21364

Preliminary Technical Data

Rev. PrB

Page 27 of 52

September 2004

Memory Write—Parallel Port

Use these specifications for asynchronous interfacing to memo-

ries (and memory-mapped peripherals) when the

ADSP-21364 is accessing external memory space.

Table 22. 8-bit Memory Write Cycle

Parameter

Min

Max

Unit

Switching Characteristics:

tALEW

ALE Pulse Width

2 × tPCLK – 2

tADAS

Address/Data 15–0 Setup Before ALE Deasserted

tPCLK – 2.5

tALERW

ALE Deasserted to Read/Write Asserted

2 × tPCLK – 2

tRWALE

Write Deasserted to ALE Asserted

H + 0.5

tWRH

Delay Between WR Rising Edge to next WR Falling Edge

F + H + tPCLK – 2

tADAH

Address/Data 15–0 Hold After ALE Deasserted

tPCLK – 0.5

tWW

WR Pulse Width

D – F – 2

tADWL

Address/Data 15–8 to WR Low

tPCLK – 1.5

tADWH

Address/Data 15–8 Hold After WR High

tDWS

Address/Data 7–0 Setup Before WR High

D – F + tPCLK – 4

tDWH

Address/Data 7–0 Hold After WR High

tDAWH

Address/Data to WR High

D – F + tPCLK – 4

D = (Data Cycle Duration = the value set by the PPDUR bits (5–1) in the PPCTL register) × tPCLK

H = tPCLK (if a hold cycle is specified, else H = 0)

F = 7 x tPCLK (if FLASH_MODE is set else F = 0)

1 On reset, ALE is an active high cycle. However, it can be configured by software to be active low.

Figure 19. Write Cycle For 8-Bit Memory Timing

AD15-8

VALID

ADDRESS

VALID ADDRESS

ADAS

AD7-0

ALE

ADAH

ADWH

ADWL

VALID DATA

DAWH

tWRH

RWALE

VALID

ADDRESS

VALID DATA

ALEW

ALERW

tWW

DWS

DWH

VALID ADDRESS

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