ADSP-21364SBBCZENG datasheet(6/52 Pages) AD

6 / 52 page

Rev. PrB

Page 6 of 52

September 2004

ADSP-21364

Preliminary Technical Data

Using the DM bus and PM buses, with one dedicated to each

memory block assures single-cycle execution with two data

transfers. In this case, the instruction must be available in the

cache.

DMA Controller

The ADSP-21364’s on-chip DMA controller allows data trans-

fers without processor intervention. The DMA controller

operates independently and invisibly to the processor core,

allowing DMA operations to occur while the core is simulta-

neously executing its program instructions. DMA transfers can

occur between the ADSP-21364’s internal memory and its serial

ports, the SPI-compatible (Serial Peripheral Interface) ports, the

IDP (Input Data Port), the Parallel Data Acquisition Port

(PDAP), or the parallel port. Twenty-five channels of DMA are

available on the ADSP-21364—two for the SPI interface, two for

memory-to-memory transfers, twelve via the serial ports, eight

via the Input Data Port, and one via the processor’s parallel

port. Programs can be downloaded to the ADSP-21364 using

DMA transfers. Other DMA features include interrupt genera-

tion upon completion of DMA transfers, and DMA chaining for

automatic linked DMA transfers.

Digital Audio Interface (DAI)

The Digital Audio Interface (DAI) provides the ability to con-

nect various peripherals to any of the SHARCs DAI pins

(DAI_P20–1).

Programs make these connections using the Signal Routing

Unit (SRU, shown in Figure 3).

The SRU is a matrix routing unit (or group of multiplexers) that

enables the peripherals provided by the DAI to be intercon-

nected under software control. This allows easy use of the DAI

associated peripherals for a much wider variety of applications

by using a larger set of algorithms than is possible with noncon-

figurable signal paths.

The DAI also includes six serial ports, two precision clock gen-

erators (PCGs), eight channels of asynchronous sample rate

converters, an input data port (IDP), an SPI port, six flag out-

puts and six flag inputs, and three timers. The IDP provides an

additional input path to the ADSP-21364 core, configurable as

either eight channels of I2S serial data or as seven channels plus

a single 20-bit wide synchronous parallel data acquisition port.

Each data channel has its own DMA channel that is indepen-

dent from the ADSP-21364's serial ports.

For complete information on using the DAI, see the ADSP-

2136x SHARC Processor Hardware Reference.

Serial Ports

The ADSP-21364 features six synchronous serial ports that pro-

vide an inexpensive interface to a wide variety of digital and

mixed-signal peripheral devices such as Analog Devices’

AD183x family of audio codecs, ADCs, and DACs. The serial

ports are made up of two data lines, a clock and frame sync. The

data lines can be programmed to either transmit or receive and

each data line has a dedicated DMA channel.

Serial ports are enabled via 12 programmable and simultaneous

receive or transmit pins that support up to 24 transmit or 24

receive channels of audio data when all six SPORTS are enabled,

or six full duplex TDM streams of 128 channels per frame.

The serial ports operate at a maximum data rate of 50M bits/s.

Serial port data can be automatically transferred to and from

on-chip memory via dedicated DMA channels. Each of the

serial ports can work in conjunction with another serial port to

provide TDM support. One SPORT provides two transmit sig-

nals while the other SPORT provides the two receive signals.

The frame sync and clock are shared.

Serial ports operate in four modes:

• Standard DSP serial mode

•Multichannel (TDM) mode

•I2S mode

• Left-justified sample pair mode

Left-justified sample pair mode is a mode where in each frame

sync cycle two samples of data are transmitted/received—one

sample on the high segment of the frame sync, the other on the

low segment of the frame sync. Programs have control over var-

ious attributes of this mode.

Figure 3. ADSP-21364 I/O Processor and Peripherals Block Diagram

PRECI SIO N CLOCK

GENERATORS (2)

SPI PORT (1 )

S ERIAL PORTS (6 )

INPUT

DATA P ORTS (8 )

TI ME RS (3)

DMA CONTROLLER

I/O PROCESSOR

P ARALLEL PO RT

GPI O FLAGS/I RQ/TIMEXP

A D D RE SS /D AT A B U S/ G P IO

CO N T R O L /G PIO

DIGITAL AUDIO INTERFACE

25 C HANNE LS

TO PROCES SOR BUSS ES AND

SYSTEM MEMO RY

IO ADDRE SS

BUS (18 )

PW M (1 6)

IO DATA

BUS (32 )

SPI PORT (1)

SRC (8 CHANNELS)

SPDIF (RX/ TX )

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