ADSP-21364SBBCZENG datasheet(19/52 Pages) AD

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ADSP-21364

Preliminary Technical Data

Rev. PrB

Page 19 of 52

September 2004

Clock Input

Clock Signals

The ADSP-21364 can use an external clock or a crystal. See

CLKIN pin description. The programmer can configure the

ADSP-21364 to use its internal clock generator by connecting

the necessary components to CLKIN and XTAL. Figure 8 shows

the component connections used for a crystal operating in fun-

damental mode. Note that the clock rate is achieved using a

16.67 MHz crystal and a PLL multiplier ratio 16:1

(CCLK:CLKIN achieves a clock speed of 266 MHz). To achieve

the full core clock rate, programs need to configure the multi-

plier bits in the PMCTL register.

Table 11. Clock Input

Parameter

333 MHz

Unit

Min

Max

Timing Requirements

tCK

CLKIN Period

181

1 Applies only for CLKCFG1–0 = 00 and default values for PLL control bits in PMCTL.

TBD2

2 Applies only for CLKCFG1–0 = 01 and default values for PLL control bits in PMCTL.

tCKL

CLKIN Width Low

7.51

TBD2

tCKH

CLKIN Width High

7.51

TBD2

tCKRF

CLKIN Rise/Fall (0.4V–2.0V)

TBD

tCCLK

3 Any changes to PLL control bits in the PMCTL register must meet core clock timing specification tCCLK.

CCLK Period

3.01

TBD

Figure 7. Clock Input

CLKIN

CKH

CKL

Figure 8. 333 MHz Operation (Fundamental Mode Crystal)

CLKIN

XTAL

NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1.

CONTACT CRYSTAL MANUFACTURER FOR DETAILS. CRYSTAL

SELECTION MUST COMPLY WITH CLKCFG1-0 = 10 OR = 01.

ADSP-21364SBBCZENG Datasheet(PDF) 19 Page - Analog Devices

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