ADSP-21364SBBCZENG datasheet(14/52 Pages) AD

14 / 52 page

Rev. PrB

Page 14 of 52

September 2004

ADSP-21364

Preliminary Technical Data

ADDRESS DATA PINS AS FLAGS

To use these pins as flags (FLAGS15–0) set (=1) bit 20 of the

SYSCTL register to disable the parallel port. Then set (=1) bits

22 to 25 in the SYSCTL register accordingly.

ADDRESS DATA MODES

The following table shows the functionality of the AD pins for

8-bit and 16-bit transfers to the parallel port. For 8-bit data

transfers, ALE latches address bits A23–A8 when asserted, fol-

lowed by address bits A7–A0 and data bits D7–D0 when

deasserted. For 16-bit data transfers, ALE latches address bits

A15–A0 when asserted, followed by data bits D15–D0 when

deasserted.

BOOT MODES

CORE INSTRUCTION RATE TO CLKIN RATIO MODES

For details on processor timing, see Timing Specifications and

Figure 5 on Page 17.

Table 4. AD15–0 to Flag Pin Mapping

AD Pin

Flag Pin

AD Pin

Flag Pin

AD0

FLAG8

AD8

FLAG0

AD1

FLAG9

AD9

FLAG1

AD2

FLAG10

AD10

FLAG2

AD3

FLAG11

AD11

FLAG3

AD4

FLAG12

AD12

FLAG4

AD5

FLAG13

AD13

FLAG5

AD6

FLAG14

AD14

FLAG6

AD7

FLAG15

AD15

FLAG7

Table 5. Address/ Data Mode Selection

EP Data

Mode

ALE

AD7–0

Function

AD15–8

Function

8-bit

Asserted

A15–8

A23–16

8-bit

Deasserted

D7–0

A7–0

16-bit

Asserted

A7–0

A15–8

16-bit

Deasserted

D7–0

D15–8

Table 6. Boot Mode Selection

BOOTCFG1–0

Booting Mode

SPI Slave Boot

SPI Master Boot

Parallel Port boot via EPROM

Table 7. Core Instruction Rate/ CLKIN Ratio Selection

CLKCFG1–0

Core to CLKIN Ratio

6:1

32:1

16:1

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