ADSP-21364SBBCZENG datasheet(31/52 Pages) AD

31 / 52 page

ADSP-21364

Preliminary Technical Data

Rev. PrB

Page 31 of 52

September 2004

Figure 22. Serial Ports

DRIVE EDGE

DAI_P20-1

SCLK (INT)

DRIVE EDGE

SCLK

DAI_P20-1

SCLK (EXT)

tDDTTE

tDDTEN

tDDTIN

DAI_P20-1

(DATA CHANNEL A/B)

DAI_P20-1

(DATA CHANNEL A/B)

DAI_P20-1

(SCLK)

DAI_P20-1

(FS)

DRIVE EDGE

SAMPLE EDGE

DATA RECEIVE— INTERNAL CLOCK

DATA RECEIVE— EXTERNAL CLOCK

DRIVE EDGE

SAMPLE EDGE

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL), SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE.

tSDRI

tHDRI

tSFSI

tHFSI

tDFSI

tHOFSI

tSCLKIW

tSDRE

tHDRE

tSFSE

tHFSE

tDFSE

tSCLKW

tHOFSE

DAI_P20-1

(DATA CHANNEL A/B)

tDDTI

DRIVE EDGE

SAMPLE EDGE

DATA TRANSMIT — INTERNAL CLOCK

tSFSI

tHFSI

tDFSI

tHOFSI

tSCLKIW

tHDTI

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL), SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE.

tDDTE

DRIVE EDGE

SAMPLE EDGE

DATA TRANSMIT — EXTERNAL CLOCK

tSFSE

tHFSE

tDFSE

tHOFSE

tSCLKW

tHDTE

DAI_P20-1

(SCLK)

DAI_P20-1

(FS)

DAI_P20-1

(DATA CHANNEL A/B)

DAI_P20-1

(SCLK)

DAI_P20-1

(FS)

DAI_P20-1

(DATA CHANNEL A/B)

DAI_P20-1

(SCLK)

DAI_P20-1

(FS)

DAI_P20-1

(DATA CHANNEL A/B)

ADSP-21364SBBCZENG Datasheet(PDF) 31 Page - Analog Devices

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