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ADSP-21364SBBCZENG Datasheet(PDF) 30 Page - Analog Devices

Part # ADSP-21364SBBCZENG
Description  SHARC Processor
PDF  52 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADSP-21364SBBCZENG Datasheet(HTML) 30 Page - Analog Devices

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Rev. PrB
|
Page 30 of 52
|
September 2004
ADSP-21364
Preliminary Technical Data
Table 26. Serial Ports—Enable and Three-State
Parameter
Min
Max
Unit
Switching Characteristics
tDDTEN
1
Data Enable from External Transmit SCLK
2
ns
tDDTTE
1
Data Disable from External Transmit SCLK
7
ns
tDDTIN
1
Data Enable from Internal Transmit SCLK
–1
ns
1 Referenced to drive edge.
Table 27. Serial Ports—External Late Frame Sync
Parameter
Min
Max
Unit
Switching Characteristics
tDDTLFSE
1
Data Delay from Late External Transmit FS or External Receive FS
with MCE = 1, MFD = 0
7
ns
tDDTENFS
1
Data Enable for MCE = 1, MFD = 01
0.5
ns
1 The tDDTLFSE and tDDTENFS parameters apply to Left-justified Sample Pair as well as DSP serial mode, and MCE = 1, MFD = 0.
Figure 21. External Late Frame Sync1
1 This figure reflects changes made to support Left-justified Sample Pair mode.
DRIVE
SAMPLE
DRIVE
DAI_P20-1
(SCLK)
DAI_P20-1
(FS)
DAI_P20-1
(DATA CHANNEL A/B)
DRIVE
SAMPLE
DRIVE
LATE EXTERNAL TRANSMIT FS
EXTERNAL RECEIVE FS WITH MCE = 1, MFD = 0
1ST BIT
2ND BIT
DAI_P20-1
(SCLK)
DAI_P20-1
(FS)
1ST BIT
2ND BIT
tHFSE/I
tSFSE/I
tDDTE/I
tDDTENFS
tDDTLFSE
tHDTE/I
tSFSE/I
tDDTE/I
tDDTENFS
tDDTLFSE
tHDTE/I
DAI_P20-1
(DATA CHANNEL A/B)
NOTE
SERIAL PORT SIGNALS (SCLK, FS, DATA CHANNEL A/B) ARE ROUTED TO THE DAI_P20-1 PINS
USING THE SRU. THE TIMING SPECIFICATIONS PROVIDED HERE ARE VALID AT THE DAI_P20-1 PINS.
tHFSE/I



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