ADSP-21364SBBCZENG datasheet(40/52 Pages) AD

40 / 52 page

Rev. PrB

Page 40 of 52

September 2004

ADSP-21364

Preliminary Technical Data

SPI Interface—Master

Table 36. SPI Interface Protocol — Master Switching and Timing Specifications

Parameter

Min

Max

Unit

Timing Requirements

tSSPIDM

Data Input Valid to SPICLK Edge (Data Input Set-up Time)

tHSPIDM

SPICLK Last Sampling Edge to Data Input Not Valid

Switching Characteristics

tSPICLKM

Serial Clock Cycle

8 × tPCLK

tSPICHM

Serial Clock High Period

4 × tPCLK

tSPICLM

Serial Clock Low Period

4 × tPCLK – 2

tDDSPIDM

SPICLK Edge to Data Out Valid (Data Out Delay Time)

tHDSPIDM

SPICLK Edge to Data Out Not Valid (Data Out Hold Time)

tSDSCIM

FLAG3–0IN (SPI Device Select) Low to First SPICLK Edge

4 × tPCLK – 2

tHDSM

Last SPICLK edge to FLAG3–0IN High

4 × tPCLK – 1

tSPITDM

Sequential Transfer Delay

4 × tPCLK – 1

Figure 33. SPI Master Timing

LSB

VALID

MSB

VALID

tSSPID M

tHSPIDM

tHDSPIDM

LSB

MSB

tHSSPIDM

tDDSPIDM

MOSI

(OUTPUT)

MISO

(INPUT)

FLAG3-0

(OUTPUT)

SPICLK

(CP = 0)

(OUTPUT)

SPICLK

(CP = 1)

(OUTPUT)

tSPICHM

tSPICLM

tSPICLKM

tSPICHM

tHDSM

tSPITDM

tHDSPIDM

LSB

VALID

LSB

MSB

VALID

tHSPIDM

tDDSPIDM

MOSI

(OUTPUT)

MISO

(INPUT)

tSSPID M

CPHASE=1

CPHASE=0

tSDSCIM

tSSPIDM

ADSP-21364SBBCZENG Datasheet(PDF) 40 Page - Analog Devices

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