ADSP-21364SBBCZENG datasheet(13/52 Pages) AD

13 / 52 page

ADSP-21364

Preliminary Technical Data

Rev. PrB

Page 13 of 52

September 2004

CLKIN

Input only

Local Clock In. Used in conjunction with XTAL. CLKIN is the ADSP-21364 clock input.

It configures the ADSP-21364 to use either its internal clock generator or an external

clock source. Connecting the necessary components to CLKIN and XTAL enables the

internal clock generator. Connecting the external clock to CLKIN while leaving XTAL

unconnected configures the ADSP-21364 to use the external clock source such as an

external clock oscillator. The core is clocked either by the PLL output or this clock input

depending on the CLKCFG1–0 pin settings. CLKIN may not be halted, changed, or

operated below the specified frequency.

XTAL

Output only2

Crystal Oscillator Terminal. Used in conjunction with CLKIN to drive an external

crystal.

CLKCFG1–0

Input only

Core/CLKIN Ratio Control. These pins set the start up clock frequency. See Table 7

for a description of the clock configuration modes.

Note that the operating frequency can be changed by programming the PLL multiplier

and divider in the PMCTL register at any time after the core comes out of reset.

RSTOUT/CLKOUT O

Output only

Local Clock Out/ Reset Out. Drives out the core reset signal to an external device.

CLKOUT can also be configured as a reset out pin.The functionality can be switched

between the PLL output clock and reset out by setting bit 12 of the PMCTREG register.

The default is reset out.

RESET

I/A

Input only

Processor Reset. Resets the ADSP-21364 to a known state. Upon deassertion, there

is a 4096 CLKIN cycle latency for the PLL to lock. After this time, the core begins

program execution from the hardware reset vector address. The RESET input must be

asserted (low) at power-up.

TCK

Input only3

Test Clock (JTAG). Provides a clock for JTAG boundary scan. TCK must be asserted

(pulsed low) after power-up or held low for proper operation of the ADSP-21364.

TMS

I/S

(pu)

Three-state with

pullup enabled

Test Mode Select (JTAG). Used to control the test state machine. TMS has a 22.5 k

Ω

internal pullup resistor.

TDI

I/S

(pu)

Three-state with

pullup enabled

Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a

22.5 k

Ω internal pullup resistor.

TDO

Three-state4

Test Data Output (JTAG). Serial scan output of the boundary scan path.

TRST

I/A

(pu)

Three-state with

pullup enabled

Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low)

after power-up or held low for proper operation of the ADSP-21364. TRST has a

22.5 k

Ω internal pullup resistor.

EMU

O (O/D)

(pu)

Three-state with

pullup enabled

Emulation Status. Must be connected to the ADSP-21364 Analog Devices processor

Tools product line of JTAG emulators target board connector only. EMU has a 22.5 k

Ω

internal pullup resistor.

VDDINT

Core Power Supply. Nominally +1.2 V dc and supplies the processor’s core processor

(13 pins on the Mini-BGA package, 32 pins on the LQFP package).

VDDEXT

I/O Power Supply. Nominally +3.3 V dc. (6 pins on the Mini-BGA package, 10 pins on

the LQFP package).

AVDD

Analog Power Supply. Nominally +1.2 V dc and supplies the processor’s internal PLL

(clock generator). This pin has the same specifications as VDDINT, except that added

filtering circuitry is required. For more information, see Power Supplies on Page 8.

AVSS

Analog Power Supply Return.

GND

Power Supply Return. (54 pins on the Mini-BGA package, 39 pins on the LQFP

package).

1 RD, WR, and ALE are three-stated (and not driven) only when RESET is active.

2 Output only is a three-state driver with its output path always enabled.

3 Input only is a three-state driver with both output path and pullup disabled.

4 Three-state is a three-state driver with pullup disabled.

Table 3. Pin Descriptions (Continued)

Type

State During &

After Reset

Function

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