 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
ADSP-21364SBBCZENG Datasheet(PDF) 29 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
ADSP-21364SBBCZENG Datasheet(HTML) 29 Page - Analog Devices |
|
|
29 / 52 page  ADSP-21364 Preliminary Technical Data Rev. PrB | Page 29 of 52 | September 2004 Serial Ports To determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay and frame sync setup and hold, 2) data delay and data setup and hold, and 3) SCLK width. Serial port signals (SCLK, FS, DxA,/DxB) are routed to the DAI_P20–1 pins using the SRU. Therefore, the timing specifica- tions provided below are valid at the DAI_P20–1 pins. Table 24. Serial Ports—External Clock Parameter Min Max Unit Timing Requirements tSFSE 1 FS Setup Before SCLK (Externally Generated FS in either Transmit or Receive Mode) 2.5 ns tHFSE 1 FS Hold After SCLK (Externally Generated FS in either Transmit or Receive Mode) 2.5 ns tSDRE 1 Receive Data Setup Before Receive SCLK 2.5 ns tHDRE 1 Receive Data Hold After SCLK 2.5 ns tSCLKW SCLK Width 24 ns tSCLK SCLK Period 48 ns Switching Characteristics tDFSE 2 FS Delay After SCLK (Internally Generated FS in either Transmit or Receive Mode) 7 ns tHOFSE 2 FS Hold After SCLK (Internally Generated FS in either Transmit or Receive Mode) 2 ns tDDTE 2 Transmit Data Delay After Transmit SCLK 7 ns tHDTE 2 Transmit Data Hold After Transmit SCLK 2 ns 1 Referenced to sample edge. 2 Referenced to drive edge. Table 25. Serial Ports—Internal Clock Parameter Min Max Unit Timing Requirements tSFSI 1 FS Setup Before SCLK (Externally Generated FS in either Transmit or Receive Mode) 7 ns tHFSI 1 FS Hold After SCLK (Externally Generated FS in either Transmit or Receive Mode) 2.5 ns tSDRI 1 Receive Data Setup Before SCLK 7 ns tHDRI 1 Receive Data Hold After SCLK 2.5 ns Switching Characteristics tDFSI 2 FS Delay After SCLK (Internally Generated FS in Transmit Mode) 3 ns tHOFSI 2 FS Hold After SCLK (Internally Generated FS in Transmit Mode) –1.0 ns tDFSI 2 FS Delay After SCLK (Internally Generated FS in Receive or Mode) 3 ns tHOFSI 2 FS Hold After SCLK (Internally Generated FS in Receive Mode) –1.0 ns tDDTI 2 Transmit Data Delay After SCLK 3 ns tHDTI 2 Transmit Data Hold After SCLK –1.0 ns tSCLKIW Transmit or Receive SCLK Width 0.5tSCLK – 2 0.5tSCLK + 2 ns 1 Referenced to the sample edge. 2 Referenced to drive edge. |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
