ADSP-21364SBBCZENG datasheet(38/52 Pages) AD

38 / 52 page

Rev. PrB

Page 38 of 52

September 2004

ADSP-21364

Preliminary Technical Data

SPDIF Receiver

The following sections describe timing as it relates to the SPDIF

receiver.

Internal Digital PLL Mode

In internal Digital Phase-locked Loop mode the internal PLL

(Digital PLL) generates the 512 × Fs clock.

Table 34. SPDIF Receiver Internal Digital PLL Mode Timing

Parameter

Min

Max

Unit

Switching Characteristics

tDFSI

LRCLK Delay After SCLK

tHOFSI

LRCLK Hold After SCLK

–2

tDDTI

Transmit Data Delay After SCLK

tHDTI

Transmit Data Hold After SCLK

–2

tSCLKIW

Transmit SCLK Width

tCCLK

Core Clock Period

1 SCLK frequency is 64 x FS where FS = the frequency of LRCLK.

Figure 31. SPDIF Receiver Internal Digital PLL Mode Timing

DRIVE EDGE

SAMPLE EDGE

DAI_P20-1

(SCLK)

DAI_P20-1

(FS)

DAI_P20-1

(DATA CHANNEL A/B)

tSCLKIW

tDFSI

tDDTI

tHOFSI

tHDTI

tSFSI

tHFSI

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