ADSP-21364SBBCZENG datasheet(36/52 Pages) AD

36 / 52 page

Rev. PrB

Page 36 of 52

September 2004

ADSP-21364

Preliminary Technical Data

SPDIF Transmitter

Serial data input to the SPDIF transmitter can be formatted as

left justified, I2S or right justified with word widths of 16, 18, 20,

or 24 bits. The following sections provide timing for the

transmitter.

SPDIF Transmitter—Serial Input Waveforms

Figure 27 shows the right-justified mode. LRCLK is HI for the

left channel and LO for the right channel. Data is valid on the

rising edge of SCLK. The MSB is delayed 12-bit clock periods

(in 20-bit output mode) or 16-bit clock periods (in 16-bit output

mode) from an LRCLK transition, so that when there are 64

SCLK periods per LRCLK period, the LSB of the data will be

right-justified to the next LRCLK transition.

Figure 28 shows the default I2S-justified mode. LRCLK is LO

for the left channel and HI for the right channel. Data is valid on

the rising edge of SCLK. The MSB is left-justified to an LRCLK

transition but with a single SCLK period delay.

Figure 29 shows the left-justified mode. LRCLK is HI for the left

channel and LO for the right channel. Data is valid on the rising

edge of SCLK. The MSB is left-justified to an LRCLK transition

with no MSB delay.

Figure 27. Right-Justified Mode

LRCLK

SCLK

SDATA

LEFT CHANNEL

RIGHT CHANNEL

MSB-1

MSB-2

LSB+2 LSB+1

LSB

MSB

MSB-1

MSB-2

LSB+2

LSB+1

LSB

MSB

Figure 28. I2S-Justified Mode

MSB-1

MSB-2

LSB+2 LSB+1

LSB

LRCLK

SCLK

SDATA

LEFT CHANNEL

RIGHT CHANNEL

MSB

MSB-1

MSB-2

LSB+2

LSB+1

LSB

MSB

Figure 29. Left-Justified Mode

LRCLK

SCLK

SDATA

LEFT CHANNEL

RIGHT CHANNEL

MSB-1

MSB-2

LSB+2

LSB+1

LSB

MSB

MSB-1

MSB-2

LSB+2

LSB+1

LSB

MSB

MSB+1

MSB

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