ADSP-21364SBBCZENG datasheet(39/52 Pages) AD

39 / 52 page

ADSP-21364

Preliminary Technical Data

Rev. PrB

Page 39 of 52

September 2004

External PLL Mode

In External PLL Mode internal Digital PLL is disabled and the

receiver runs on the PLL that is connected to the processor

externally. This external PLL generates the 512 x Fs clock

(MCLK) from the reference clock (LRCLK) and gives it to

SPDIF receiver.

Table 35. SPDIF Receiver External PLL Mode Timing

Parameter

Min

Max

Unit

Timing Requirements

tMCP

MCLK Period

FMCLK

MCLK Frequency (1/tMCP)100

MHz

tBDM

SCLK Propagation Delay from MCLK to the Falling Edge

tLDM

LRCLK Propagation Delay From MCLK

tDDP

Data Propagation Delay From MCLK

tDDS

Data Output Setup To SCLK

1/2 SCLK Period

tDDH

Data Output Hold From SCLK

1/2 SCLK Period

Figure 32. SPDIF Receiver External PLL Mode Timing

tLDM

tBDM

tDDS

MSB

tDDH

MCLK INPUT

(NOT TO SCALE)

BCLK OUTPUT

LRCLK

OUTPUT

SDATA OUTPUT

I2S-JUSTIFIED

MODE

tDDP

tDDS

tDDH

tDDP

MSB

LSB

tDDH

tDDS

SDATA OUTPUT

RIGHT-JUSTIFIED

MODE

ADSP-21364SBBCZENG Datasheet(PDF) 39 Page - Analog Devices

ADSP-21364SBBCZENG Datasheet(HTML) 39 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52

Datasheet Download

Link URL