ADSP-21364SBBCZENG datasheet(41/52 Pages) AD

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ADSP-21364

Preliminary Technical Data

Rev. PrB

Page 41 of 52

September 2004

SPI Interface—Slave

Table 37. SPI Interface Protocol —Slave Switching and Timing Specifications

Parameter

Min

Max

Unit

Timing Requirements

tSPICLKS

Serial Clock Cycle

4 × tPCLK

tSPICHS

Serial Clock High Period

2 × tPCLK

tSPICLS

Serial Clock Low Period

2 × tPCLK – 2

tSDSCO

SPIDS Assertion to First SPICLK Edge

CPHASE = 0

CPHASE = 1

2 × tPCLK

tHDS

Last SPICLK Edge to SPIDS Not Asserted, CPHASE = 0

2 × tPCLK

tSSPIDS

Data Input Valid to SPICLK edge (Data Input Set-up Time)

tHSPIDS

SPICLK Last Sampling Edge to Data Input Not Valid

tSDPPW

SPIDS Deassertion Pulse Width (CPHASE=0)

2 × tPCLK

Switching Characteristics

tDSOE

SPIDS Assertion to Data Out Active

tDSDHI

SPIDS Deassertion to Data High Impedance

tDDSPIDS

SPICLK Edge to Data Out Valid (Data Out Delay Time)

9.4

tHDSPIDS

SPICLK Edge to Data Out Not Valid (Data Out Hold Time)

2 × tPCLK

tDSOV

SPIDS Assertion to Data Out Valid (CPHASE=0)

5 × tPCLK

Figure 34. SPI Slave Timing

tHSPIDS

tDDSPIDS

tDSDHI

LSB

MSB

MSB VALID

tDSOE

tDDSPIDS

tHD LSB S

MISO

(OUTPUT)

MOSI

(INPUT)

tSSPIDS

SPIDS

(INPUT)

SPICLK

(CP = 0)

(INPUT)

SPICLK

(CP = 1)

(INPUT)

tSDSCO

tSPIC HS

tSPICLS

tSPICLKS

tHDS

tSPICHS

tSSPIDS

tHSPIDS

tDSDHI

LSB VALID

MSB

MSB VALID

tDSO E

tDDSPIDS

MISO

(OUTPUT)

MOSI

(INPUT)

tSSPIDS

LSB VALID

LSB

CPHASE=1

CPHASE=0

tSDPPW

tDSOV

tHDLSBS

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