ADSP-21364SBBCZENG datasheet(26/52 Pages) AD

26 / 52 page

Rev. PrB

Page 26 of 52

September 2004

ADSP-21364

Preliminary Technical Data

Table 21. 16-bit Memory Read Cycle

Parameter

Min

Max

Unit

Timing Requirements

tDRS

Address/Data 15–0 Setup Before RD High

3.3

tDRH

Address/Data 15–0 Hold After RD High

Switching Characteristics

tALEW

ALE Pulse Width

2 × tPCLK – 2

tADAS

Address/Data 15–0 Setup Before ALE Deasserted

tPCLK – 2.5

tALERW

ALE Deasserted to Read Asserted

2 × tPCLK – 2

tRRH

Delay Between RD Rising Edge to Next Falling Edge.

H + tPCLK – 1

tRWALE

Read Deasserted to ALE Asserted

F + H + 0.5

tRDDRV

RD Address Drive After Read High

F + H + tPCLK – 1

tADAH

Address/Data 15–0 Hold After ALE Deasserted

tPCLK – 0.8

tALEHZ

ALE Deasserted to Address/Data15–0 in High Z

tPCLK – 0.8

tRW

RD Pulse Width

D – 2

D = (Data Cycle Duration = the value set by the PPDUR bits (5–1) in the PPCTL register) × tPCLK

H = tPCLK (if a hold cycle is specified, else H = 0)

F = 7 x tPCLK (if FLASH_MODE is set else F = 0)

1 On reset, ALE is an active high cycle. However, it can be configured by software to be active low.

Figure 18. Read Cycle For 16-Bit Memory Timing

AD15-0

DRS

DRH

tRDDRV

ALEHZ

ADAH

ADAS

VALID ADDRESS

VALID DATA

VALID

ADDRESS

ALEW

tRW

ALERW

tRWALE

RRH

ALE

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