ADSP-21364SBBCZENG datasheet(34/52 Pages) AD

34 / 52 page

Rev. PrB

Page 34 of 52

September 2004

ADSP-21364

Preliminary Technical Data

Sample Rate Converter—Serial Input Port

The SRC input signals (SCLK, FS, and SDATA) are routed from

the DAI_P20–1 pins using the SRU. Therefore, the timing spec-

ifications provided in Table 30 are valid at the DAI_P20–1 pins.

Table 30. SRC, Serial Input Port

Parameter

Min

Max

Unit

Timing Requirements

tSIFS

FS Setup Before SCLK Rising Edge

tSIHFS

FS Hold After SCLK Rising Edge

5.5

tSISD

SData Setup Before SCLK Rising Edge

tSIHD

SData Hold After SCLK Rising Edge

5.5

tIDPCLKW

Clock Width

tIDPCLK

Clock Period

1 DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG's input can be either CLKIN or any of the DAI pins.

Figure 25. SRC Serial Input Port Timing

DAI_P20-1

(SCLK)

DAI_P20-1

(FS)

SAMPLE EDGE

tSISD

tSIHD

tSISFS

tSIHFS

tIDPCLKW

DAI_P20-1

(SDATA)

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