ADSP-21364SBBCZENG datasheet(42/52 Pages) AD

42 / 52 page

Rev. PrB

Page 42 of 52

September 2004

ADSP-21364

Preliminary Technical Data

JTAG Test Access Port and Emulation

Table 38. JTAG Test Access Port and Emulation

Parameter

Min

Max

Unit

Timing Requirements

tTCK

TCK Period

tCK

tSTAP

TDI, TMS Setup Before TCK High

tHTAP

TDI, TMS Hold After TCK High

tSSYS

System Inputs Setup Before TCK Low

tHSYS

System Inputs Hold After TCK Low

tTRSTW

TRST Pulse Width

4tCK

Switching Characteristics

tDTDO

TDO Delay From TCK Low

tDSYS

System Outputs Delay After TCK Low

1 System Inputs = AD15–0, SPIDS, CLKCFG1–0, RESET, BOOTCFG1–0, MISO, MOSI, SPICLK, DAI_Px, FLAG3–0.

2 System Outputs = MISO, MOSI, SPICLK, DAI_Px, AD15–0, RD, WR, FLAG3–0, CLKOUT, EMU, ALE.

Figure 35. IEEE 1149.1 JTAG Test Access Port

TCK

TMS

TDI

TDO

SYSTEM

INPUTS

SYSTEM

OUTPUTS

tSTAP

tTCK

tHTAP

tDTDO

tSSYS

tHSYS

tDSYS

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