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ADSP-21364SBBCZENG Datasheet(PDF) 21 Page - Analog Devices |
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ADSP-21364SBBCZENG Datasheet(HTML) 21 Page - Analog Devices |
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21 / 52 page  ADSP-21364 Preliminary Technical Data Rev. PrB | Page 21 of 52 | September 2004 Core Timer The following timing specification applies to FLAG3 when it is configured as the core timer (CTIMER). Timer PWM_OUT Cycle Timing The following timing specification applies to Timer0, Timer1, and Timer2 in PWM_OUT (pulse width modulation) mode. Timer signals are routed to the DAI_P20–1 pins through the SRU. Therefore, the timing specifications provided below are valid at the DAI_P20–1 pins. Table 14. Core Timer Parameter Min Max Unit Switching Characteristic tWCTIM CTIMER Pulse Width 4 × tPCLK – 1 ns Figure 11. Core Timer FLAG3 (CTIMER) tWCTIM Table 15. Timer PWM_OUT Timing Parameter Min Max Unit Switching Characteristic tPWMO Timer Pulse Width Output 2 tPCLK – 1 2(231 – 1) tPCLK ns Figure 12. Timer PWM_OUT Timing DAI_P20-1 (TIMER2-0) tPWMO |
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