ADSP-21364SBBCZENG datasheet(32/52 Pages) AD

32 / 52 page

Rev. PrB

Page 32 of 52

September 2004

ADSP-21364

Preliminary Technical Data

Input Data Port (IDP)

The timing requirements for the IDP are given in Table 28.IDP

Signals (SCLK, FS, SDATA) are routed to the DAI_P20–1 pins

using the SRU. Therefore, the timing specifications provided

below are valid at the DAI_P20–1 pins.

Table 28. IDP

Parameter

Min

Max

Unit

Timing Requirements

tSIFS

FS Setup Before SCLK Rising Edge

2.5

tSIHFS

FS Hold After SCLK Rising Edge

2.5

tSISD

SData Setup Before SCLK Rising Edge

2.5

tSIHD

SData Hold After SCLK Rising Edge

2.5

tIDPCLKW

Clock Width

tIDPCLK

Clock Period

1 DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG's input can be either CLKIN or any of the DAI pins.

Figure 23. IDP Master Timing

DAI_P20-1

(SCLK)

DAI_P20-1

(FS)

SAMPLE EDGE

tSISD

tSIHD

tSISFS

tSIHFS

tSISCLKW

DAI_P20-1

(SDATA)

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