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ADSP-21364SBBCZENG Datasheet(PDF) 22 Page - Analog Devices |
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ADSP-21364SBBCZENG Datasheet(HTML) 22 Page - Analog Devices |
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22 / 52 page  Rev. PrB | Page 22 of 52 | September 2004 ADSP-21364 Preliminary Technical Data Timer WDTH_CAP Timing The following timing specification applies to Timer0, Timer1, and Timer2 in WDTH_CAP (pulse width count and capture) mode. Timer signals are routed to the DAI_P20–1 pins through the SRU. Therefore, the timing specifications provided below are valid at the DAI_P20–1 pins. DAI Pin to Pin Direct Routing For direct pin connections only (for example DAI_PB01_I to DAI_PB02_O). Table 16. Timer Width Capture Timing Parameter Min Max Unit Timing Requirement tPWI Timer Pulse Width 2 tPCLK 2(231– 1) tPCLK ns Figure 13. Timer Width Capture Timing DAI_P20-1 (TIMER2-0) tPWI Table 17. DAI Pin to Pin Routing Parameter Min Max Unit Timing Requirement tDPIO Delay DAI Pin Input Valid to DAI Output Valid 1.5 10 ns Figure 14. DAI Pin to PIN Direct Routing DAI_PN tDPIO DAI_PM |
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