ADSP-21364SBBCZENG datasheet(16/52 Pages) AD

16 / 52 page

Rev. PrB

Page 16 of 52

September 2004

ADSP-21364

Preliminary Technical Data

MAXIMUM POWER DISSIPATION

The data in this table is based on theta JA (θJA) established per

JEDEC standards JESD51-2 and JESD51-6. See Engineer-to-

Engineer note (EE-TBD) for further information. For informa-

tion on package thermal specifications, see Thermal

Characteristics on Page 44.

ABSOLUTE MAXIMUM RATINGS

ESD SENSITIVITY

TIMING SPECIFICATIONS

The ADSP-21364’s internal clock (a multiple of CLKIN) pro-

vides the clock signal for timing internal memory, processor

core, serial ports, and parallel port (as required for read/write

strobes in asynchronous access mode). During reset, program

the ratio between the processor’s internal clock frequency and

external (CLKIN) clock frequency with the CLKCFG1–0 pins.

To determine switching frequencies for the serial ports, divide

down the internal clock, using the programmable divider con-

trol of each port (DIVx for the serial ports).

The ADSP-21364’s internal clock switches at higher frequencies

than the system input clock (CLKIN). To generate the internal

clock, the processor uses an internal phase-locked loop (PLL).

This PLL-based clocking minimizes the skew between the sys-

tem clock (CLKIN) signal and the processor’s internal clock (the

clock source for the parallel port logic and I/O pads).

Max Ambient

Temp1

1 Power Dissipation greater than that listed above may cause permanent damage to the device.

For more information, see Thermal Characteristics on Page 44.

144 INT–HS

LQFP2

2 Heat slug soldered to PCB

144 INT–HS

LQFP3

3 Heat slug not soldered to PCB

136 Mini-

BGA4

4 Thermal vias in PCB

136 Mini-

BGA5

5 No thermal vias in PCB

°C

3.33W

2.10W

2.44W

2.18W

°C

2.42W

N/A

1.77W

N/A

105

°C1.21W

N/A

Parameter

Rating

Internal (Core) Supply Voltage (VDDINT)

1 Stresses greater than those listed above may cause permanent damage to the device. These

are stress ratings only; functional operation of the device at these or any other conditions

greater than those indicated in the operational sections of this specification is not implied.

Exposure to absolute maximum rating conditions for extended periods may affect device

reliability.

–0.3 V to +1.5 V

Analog (PLL) Supply Voltage (AVDD)

–0.3 V to +1.5 V

External (I/O) Supply Voltage (VDDEXT)

–0.3 V to +4.6 V

Input Voltage–0.5 V to VDDEXT

+ 0.5 V

Output Voltage Swing–0.5 V to VDDEXT

+ 0.5 V

Load Capacitance1

200 pF

Storage Temperature Range1

–65

°C to +150°C

Junction Temperature under Bias

125

°C

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily

accumulate on the human body and test equipment and can discharge without detection.

Although the ADSP-21364 features proprietary ESD protection circuitry, permanent damage may

occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD

precautions are recommended to avoid performance degradation or loss of functionality.

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