ADSP-21364SBBCZENG datasheet(28/52 Pages) AD

28 / 52 page

Rev. PrB

Page 28 of 52

September 2004

ADSP-21364

Preliminary Technical Data

Table 23. 16-bit Memory Write Cycle

Parameter

Min

Max

Unit

Switching Characteristics

tALEW

ALE Pulse Width

2 × tPCLK – 2

tADAS

Address/Data 15–0 Setup Before ALE Deasserted

tPCLK – 2.5

tALERW

ALE Deasserted to Write Asserted

2 × tPCLK – 2

tRWALE

Write Deasserted to ALE Asserted

H + 0.5

tWRH

Delay Between WR Rising Edge to next WR Falling Edge

F + H + tPCLK – 2

tADAH

Address/Data 15–0 Hold After ALE Deasserted

tPCLK – 0.5

tWW

WR Pulse Width

D – F – 2

tALEHZ

ALE Deasserted to Address/Data15–0 in High Z

tPCLK – 1.5

tDWS

Address/Data 15–0 Setup Before WR High

D – F + tPCLK – 4

tDWH

Address/Data 15–0 Hold After WR High

D = (Data Cycle Duration = the value set by the PPDUR bits (5–1) in the PPCTL register) × tPCLK

H = tPCLK (if a hold cycle is specified, else H = 0)

F = 7 x tPCLK (if FLASH_MODE is set else F = 0)

1 On reset, ALE is an active high cycle. However, it can be configured by software to be active low.

Figure 20. Write Cycle For 16-Bit Memory Timing

AD15-0

VALID

ADDRESS

VALID DATA

ADAS

ALE

ADAH

tWRH

RWALE

ALEW

ALERW

tWW

DWS

DWH

VALID DATA

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