ADSP-21364SBBCZENG datasheet(20/52 Pages) AD

20 / 52 page

Rev. PrB

Page 20 of 52

September 2004

ADSP-21364

Preliminary Technical Data

Reset

Interrupts

The following timing specification applies to the FLAG0,

FLAG1, and FLAG2 pins when they are configured as IRQ0,

IRQ1, and IRQ2 interrupts. Also applies to DAI_P20–1 pins

when configured as interrupts

Table 12. Reset

Parameter

Min

Max

Unit

Timing Requirements

tWRST

RESET Pulse Width Low

4tCK

tSRST

RESET Setup Before CLKIN Low

1 Applies after the power-up sequence is complete. At power-up, the processor's internal phase-locked loop requires no more than 100 µs while RESET is low, assuming

stable VDD and CLKIN (not including start-up time of external clock oscillator).

Figure 9. Reset

CLKIN

RESET

tWRST

tSRST

Table 13. Interrupts

Parameter

Min

Max

Unit

Timing Requirement

tIPW

IRQx Pulse Width

2 × tPCLK + 2

Figure 10. Interrupts

DAI_P20-1

FLAG2-0

(IRQ2-0)

tIPW

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