ADSP-21364SBBCZENG datasheet(35/52 Pages) AD

35 / 52 page

ADSP-21364

Preliminary Technical Data

Rev. PrB

Page 35 of 52

September 2004

Sample Rate Converter—Serial Output Port

For the serial output port, the frame-sync is an input and it

should meet setup and hold times with regard to SCLK on the

output port. The serial data output, SDATA, has a hold time

and delay specification with regard to SCLK. Note that SCLK

rising edge is the sampling edge and the falling edge is the drive

edge.

Table 31. SRC, Serial Output Port

Parameter

Min

Max

Unit

Timing Requirements

tSIFS

FS Setup Before SCLK Rising Edge

tSIHFS

FS Hold Before SCLK Rising Edge

5.5

tSRCTDD

Transmit Data Delay After SCLK Falling Edge

tSRCTDH

Transmit Data Hold After SCLK Falling Edge

1 DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG's input can be either CLKIN or any of the DAI pins.

Figure 26. SRC Serial Output Port Timing

DAI_P20-1

(SCLK)

DAI_P20-1

(FS)

SAMPLE EDGE

tSIFS

tSIHFS

tSISCLKW

DAI_P20-1

(SDATA)

tSRCTDD

tSRCTDH

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