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MCS11 Datasheet(PDF) 46 Page - PADAUK Technology. |
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MCS11 Datasheet(HTML) 46 Page - PADAUK Technology. |
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46 / 108 page  MCS11 ADC-Type Enhanced FPPA TM Controller ©Copyright 2018, PADAUK Technology Co. Ltd Page 46 of 108 PDK-DS-MCS11_v020 – Apr. 20, 2018 5-13. IO Pins Other than PA5, all the pins can be independently set into two states output or input by configuring the data registers (pa, pb), control registers (pac, pbc) and pull-high registers (paph, pbph). All these pins have Schmitt-trigger input buffer and output driver with CMOS level. When it is set to output low, the pull-up resistor is turned off automatically. If user wants to read the pin state, please notice that it should be set to input mode before reading the data port; if user reads the data port when it is set to output mode, the reading data comes from data register, NOT from IO pad. As an example, Table 6 shows the configuration table of bit 0 of port A. The hardware diagram of IO buffer is also shown as Fig. 5-13-1. Table 6 PA0 Configuration Table Fig. 5-13-1 Hardware diagram of IO buffer pa.0 pac.0 paph.0 Description X 0 0 Input without pull-up resistor X 0 1 Input with pull-up resistor 0 1 X Output low without pull-up resistor 1 1 0 Output high without pull-up resistor 1 1 1 Output high with pull-up resistor D Q (weak P-MOS) PAD WR pull-high latch WR data latch WR control latch RD pull-high latch RD control latch RD Port D Q D Q M U X pull-high latch Data latch Control latch Data Bus Q1 Analog Module padier.x or pbdier.x Wakeup module Interrupt module (PA0,PB0 only) D Q (weak P-MOS) PAD WR pull-high latch WR data latch WR control latch RD pull-high latch RD control latch RD Port D Q D Q M U X pull-high latch Data latch Control latch Data Bus Q1 Analog Module padier.x or pbdier.x Wakeup module Interrupt module (PA0,PB0 only) |
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