MCS11 datasheet(65/108 Pages) PADAUK

65 / 108 page

MCS11

ADC-Type Enhanced FPPA

TM Controller

Page 65 of 108

PDK-DS-MCS11_v020 – Apr. 20, 2018

6-4. Clock Mode Register (clkmd), IO address = 0x03

Bit

Reset R/W

Description

7 – 5

111

R/W

System clock selection:

Type 0, clkmd[3]=0

Type 1, clkmd[3]=1

000: IHRC/4

001: IHRC/2

010: reserved

011: EOSC/4

100: EOSC/2

101: EOSC

110: ILRC/4

111: ILRC (default)

000: IHRC/16

001: IHRC/8

010: reserved

011: IHRC/32

100: IHRC/64

101: EOSC/8

11x: reserved

R/W IHRC oscillator Enable. 0 / 1: disable / enable

Clock Type Select. This bit is used to select the clock type in bit [7:5].

0 / 1: Type 0 / Type 1.

R/W ILRC Enable. 0 / 1: disable / enable

R/W Watch Dog Enable. 0 / 1: disable / enable

R/W Pin PA5/RESET# function. 0 / 1: PA5 / RESET#.

6-5 Register Option Register (rop), IO address = 0x3e

Bit

Reset

R/W

Description

7 – 4

Reserved.

PWMG resolution selection

0: 11-bit

1: 10-bit

Option for Timer16 clock pre-divider selection. Please see the t16m register.

Option for external interrupt 1 pin selection.

Option for external interrupt 0 pin selection.

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