MCS11 datasheet(74/108 Pages) PADAUK

74 / 108 page

MCS11

ADC-Type Enhanced FPPA

TM Controller

Page 74 of 108

PDK-DS-MCS11_v020 – Apr. 20, 2018

6-29. Timer2 Scalar Register (tm2s), IO address = 0x37

Bit

Reset

R/W

Description

Reserved.

6 – 5

Timer2 clock pre-scalar.

00 : /1

01 : /4

10 : /16

11 : /64

4 – 0

00000

Timer2 clock scalar.

6-30. Timer2 Bound Register (tm2b), IO address = 0x09

Bit

Reset

R/W

Description

7 – 0

0x00

Timer2 bound register.

6-31. Hall Comparator Control Register (hcc), IO address = 0x2a

Bit

Reset

R/W

Description

R/W

Enable Hall comparator.

0 / 1 : disable / enable

When this bit is set to enable, please also set the corresponding analog input pins to be

digital disable to prevent IO leakage.

Comparison result of Hall comparator 1 (HC_1), output: HC_Out1.

Comparison result of Hall comparator 2 (HC_2), output HC_Out2.

HC_Out

Reversed

2 – 0

R/W

Output to PA5 and interrupt source of the hall comparator

0x00: None output to PA5, interrupt source = HC_Out1

0x01: None output to PA5, interrupt source = HC_Out2

0x02: None output to PA5, interrupt source = HC_Out

0x03: HC_Out1 to PA5, interrupt source = HC_Out1

0x04: HC_Out2 to PA5, interrupt source = HC_Out2

0x05: HC_Out to PA5, interrupt source = HC_Out

Others: reversed

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