MCS11 datasheet(67/108 Pages) PADAUK

67 / 108 page

MCS11

ADC-Type Enhanced FPPA

TM Controller

Page 67 of 108

PDK-DS-MCS11_v020 – Apr. 20, 2018

6-8. Timer16 mode Register (t16m), IO address = 0x06

Bit

Reset

R/W

Description

7 - 5

000

R/W

Timer Clock source selection.

000: Timer16 is disabled.

001: CLK (system clock)

010: reserved

011: PA4

100: IHRC

101: EOSC

110: ILRC

111: PA0

Others: Timer16 is disabled.

4 – 3

R/W

rop.2=0

Timer16 clock pre-divider. 00: /1

01: /4

10: /16

11: /64

rop.2=1

Timer16 clock pre-divider. 00: /2

01: /8

10: /32

11: /128

2 – 0

000

R/W

Interrupt source selection. Interrupt event happens when selected bit goes high.

0 : bit 8 of Timer16

1 : bit 9 of Timer16

2 : bit 10 of Timer16

3 : bit 11 of Timer16

4 : bit 12 of Timer16

5 : bit 13 of Timer16

6 : bit 14 of Timer16

7 : bit 15 of Timer16

Where, rop is the 0x3e register optional register.

6-9. General Data register for IO (gdio), IO address = 0x07

Bit

Reset

R/W

Description

7 – 0

R/W

General data for IO. This port is the general data buffer in IO space and cleared when

POR or LVD, and it will KEEP the old values when reset from watch-dog timeout. It can

perform the IO operation, like wait0 gdio.x, wait1 gdio.x and tog gdio.x to replace of

operations which instructions are supported in memory space (ex: wait1 mem; wait0

mem; tog mem).

6-10. Multiplier Operand Register (mulop), IO address = 0x08

Bit

Reset

R/W

Description

7 – 0

R/W

Operand for hardware multiplication operation.

6-11. Multiplier Result High Byte Register (mulrh), IO address = 0x09

Bit

Reset

R/W

Description

7 – 0

High byte result of multiplication operation (read only).

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