MCS11 datasheet(76/108 Pages) PADAUK

76 / 108 page

MCS11

ADC-Type Enhanced FPPA

TM Controller

Page 76 of 108

PDK-DS-MCS11_v020 – Apr. 20, 2018

6-35 PWM Generator Scalar Register (pwms), IO address = 0x31

Bit

Reset

R/W

Description

R/W

PWM interrupt mode.

0: Generate interrupt when counter is 0.

1: Generate interrupt when counter matches the duty value

6 – 5

R/W

PWM generator clock pre-scalar.

00 : /1

01 : /4

10 : /16

11 : /64

4 – 0

R/W

PWM generator clock divider.

6-36 PWM Counter Upper Bound High Register (pwmcubh), IO address = 0x1a

Bit

Reset

R/W

Description

7 - 0

8’h00

Bit[10:3] of PWM counter upper bound.

6-37 PWM Counter Upper Bound Low Register (pwmcubl), IO address = 0x1b

Bit

Reset

R/W

Description

7 – 5

000

Bit[2:0] of PWM counter upper bound.

4 – 0

Reserved

6-38 PWM Duty Value High Register (pwmdth), IO address = 0x32

Bit

Reset

R/W

Description

7 - 0

8’h00

Duty values bit[10:3] of PWM generator.

6-39 PWM Duty Value Low Register (pwmdtl), IO address = 0x33

Bit

Reset

R/W

Description

7 - 5

000

Duty values bit[2:0] of PWM generator.

4 – 0

Reserved

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