MCS11 datasheet(81/108 Pages) PADAUK

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MCS11

ADC-Type Enhanced FPPA

TM Controller

Page 81 of 108

PDK-DS-MCS11_v020 – Apr. 20, 2018

6-49 MISC Register (misc), IO address = 0x3b

Bit

Reset

R/W

Description

Reserved

Enable extremely low current for 32KHz crystal oscillator AFTER oscillation.

0: Normal.

1: Low driving current for 32KHz crystal oscillator.

Enable fast Wake-up. Fast wake-up is NOT supported when EOSC is enabled.

0: Normal wake-up.

The wake-up time is 1024 ILRC clocks

1: Fast wake-up. (for

The wake-up time is 128 CLKs (system clock) + oscillator stable time.

If wake-up from STOPEXE suspend, there is no oscillator stable time;

If wake-up from STOPSYS suspend, it will be IHRC or ILRC stable time from

power-on.

Please notice that the clock source will be switched to system clock

(for example: 4MHz) when fast wakeup is enabled, therefore,

it is recommended to turn off the watchdog timer before enabling the fast wakeup

and turn on the watchdog timer after disabling the fast wakeup.

Reserved.

Recover time from LVD reset.

0: Normal. The system will take about 1024 ILRC clocks to boot up from LVD reset.

1: Fast. The system will take about 64 ILRC clocks to boot up from LVD reset.

Disable LVD function.

0 / 1 : Enable / Disable

1 – 0

Watch dog time out period

00: 2048 ILRC clock period

01: 4096 ILRC clock period

10: 16384 ILRC clock period

11:

256 ILRC clock period

6-50 FPPA Reset Register, IO address = 0x3f

Bit

Reset

R/W

Description

Reset FPP7. This bit will be cleared automatically after resetting FPP7.

Reset FPP6. This bit will be cleared automatically after resetting FPP6.

Reset FPP5. This bit will be cleared automatically after resetting FPP5.

Reset FPP4. This bit will be cleared automatically after resetting FPP4.

Reset FPP3. This bit will be cleared automatically after resetting FPP3.

Reset FPP2. This bit will be cleared automatically after resetting FPP2.

Reset FPP1. This bit will be cleared automatically after resetting FPP1.

Reset FPP0. This bit will be cleared automatically after resetting FPP0.

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