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MCS11 Datasheet(PDF) 48 Page - PADAUK Technology. |
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MCS11 Datasheet(HTML) 48 Page - PADAUK Technology. |
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48 / 108 page  MCS11 ADC-Type Enhanced FPPA TM Controller ©Copyright 2018, PADAUK Technology Co. Ltd Page 48 of 108 PDK-DS-MCS11_v020 – Apr. 20, 2018 5-15. Hall Comparator The hall comparator is built by hardware circuitry HC_1 and HC_2. PA4 is the plus input for both HC_1 and HC_2, PA0, PA1 and PA2 are the minus input by option. The hall comparator output (HC_Out) is combined by HC_Out1 and HC_Out2. HC_Out can be output to PA5 and internal used. The hall comparator adjust registers (hc1a and hc2a ) are used to control the offset value of HC_1 and HC_2 in order to optimize the system performance. Fig. 5-15-1 The hardware diagram of Hall comparator HC_1 HC_2 PA0 PA1 PA2 PA4 Band-gap 1.2V HC_Out1 HC_Out2 0 1 A M U X + - + - A M U X 00 10 01 11 Hall Comparator 1 Hall Comparator 2 hc1a.7 hc1a. [7:6] M U X M U X hcc [2:0] hcc [2:0] PA5 Hall comparator interrupt HC_1 HC_2 PA0 PA1 PA2 PA0 PA1 PA2 PA4 Band-gap 1.2V HC_Out1 HC_Out2 0 1 A M U X + - + - A M U X 00 10 01 11 Hall Comparator 1 Hall Comparator 2 hc1a.7 hc1a. [7:6] M U X M U X hcc [2:0] hcc [2:0] PA5 Hall comparator interrupt |
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