MCS11 datasheet(71/108 Pages) PADAUK

71 / 108 page

MCS11

ADC-Type Enhanced FPPA

TM Controller

Page 71 of 108

PDK-DS-MCS11_v020 – Apr. 20, 2018

6-17. Port A Data Register (pa), IO address = 0x10

Bit

Reset

R/W

Description

7 – 0

R/W

Data register for Port A.

6-18. Port A Control Register (pac), IO address = 0x11

Bit

Reset

R/W

Description

7 - 0

8’h00

R/W

Port A control registers. This register is used to define input mode or output mode for

each corresponding pin of port A.

0 / 1: input / output

Please note that PA5 can be INPUT or OUTPUT LOW ONLY, the output state will be

tri-state when PA5 is programmed into output mode with data 1.

6-19. Port A Pull-High Register (paph), IO address = 0x12

Bit

Reset

R/W

Description

7 - 0

8’h00

R/W

Port A pull-high register. This register is used to enable the internal pull-high device on

each corresponding pin of port A and this pull high function is active only for input mode.

0 / 1 : disable / enable

Please note that PA5 does NOT have pull-up resistor.

6-20. Port B Data Register (pb), IO address = 0x14

Bit

Reset

R/W

Description

7 – 0

R/W

Data register for Port B.

6-21. Port B Control Register (pbc), IO address = 0x15

Bit

Reset

R/W

Description

7 - 0

8’h00

R/W

Port B control register. This register is used to define input mode or output mode for each

corresponding pin of port B.

0 / 1: input / output

6-22. Port B Pull-High Register (pbph), IO address = 0x16

Bit

Reset

R/W

Description

7 - 0

8’h00

R/W

Port B pull-high register. This register is used to enable the internal pull-high device on

each corresponding pin of port B.

0 / 1 : disable / enable

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