MCS11 datasheet(37/108 Pages) PADAUK

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MCS11

ADC-Type Enhanced FPPA

TM Controller

Page 37 of 108

PDK-DS-MCS11_v020 – Apr. 20, 2018

5-8. 16-bit Timer (Timer16)

MCS11 provides a 16-bit hardware timer (Timer16) and its clock source may come from system clock (CLK),

external crystal oscillator (EOSC), internal high RC oscillator (IHRC), internal low RC oscillator (ILRC), PA0 or

PA4.

Before sending clock to the 16-bit counter, a pre-scaling logic with divided-by-1, 4, 16 or 64 is

selectable for wide range counting. The 16-bit counter performs up-counting operation only, the counter initial

values can be stored from data memory by issuing the stt16 instruction and the counting values can be loaded

to data memory by issuing the ldt16 instruction. The interrupt request from Timer16 will be triggered by the

selected bit which comes from bit[15:8] of this 16-bit counter, rising edge or falling edge can be optional

chosen by register integs.4. The hardware diagram of Timer16 is shown as Fig. 5-8-1.

Fig. 5-8-1 Hardware diagram of Timer16

When using the Timer16, the syntax for Timer16 has been defined in the .INC file. There are three parameters

to define the Timer16 using; 1

st parameter is used to define the clock source of Timer16, 2nd parameter is used

to define the pre-scalar and the 3

rd one is to define the interrupt source.

T16M

IO_RW

0x06

$ 7~5:

STOP, SYSCLK, X, X, PA4, IHRC, EOSC, ILRC, PA0

// 1

st par.

$ 4~3:

/1, /4, /16, /64

// 2

nd par.

$ 2~0:

BIT8, BIT9, BIT10, BIT11, BIT12, BIT13, BIT14, BIT15

// 3

rd par.

User can choose the proper parameters of T16M to meet system requirement, examples as below:

T16M

SYSCLK, /64, BIT15;

// choose (SYSCLK/64) as clock source, every 2^16 clock to set INTRQ.2=1

// if system clock SYSCLK = IHRC / 2 = 8 MHz

// SYSCLK/64 = 8 MHz/64 = 8 uS, about every 524 mS to generate INTRQ.2=1

T16M

EOSC, /1, BIT13;

// choose (EOSC/1) as clock source, every 2^14 clock cycle to generate INTRQ.2=1

// if EOSC=32768 Hz, 32768 Hz/(2^14) = 2Hz, every 0.5S to generate INTRQ.2=1

t16m[7:5]

CLK

IHRC

EOSC

ILRC

PA0

PA4

Pre-

scalar

1, 4,

16, 64

t16m[4:3]

16-bit

counter

Bit[15:0]

To set

interrupt

request flag

Data Bus

stt16 command

t16m[2:0]

Bit[15:8]

DATA Memory

ldt16 command

integs.4

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