MCS11 datasheet(68/108 Pages) PADAUK

68 / 108 page

MCS11

ADC-Type Enhanced FPPA

TM Controller

Page 68 of 108

PDK-DS-MCS11_v020 – Apr. 20, 2018

6-12. External Oscillator setting Register (eoscr), IO address = 0x0a

Bit

Reset

R/W

Description

Enable crystal oscillator.

0 / 1 : Disable / Enable

6 – 5

External oscillator selection.

00 : reserved

01 : Low driving current, for lower frequency, ex: 32KHz crystal oscillator

10 : Middle driving current, for middle frequency, ex: 1MHz crystal oscillator

11 : High driving current, for higher frequency, ex: 4MHz crystal oscillator

4 – 1

Reserved. Please keep 0.

Power down both band-gap and LVD hardware modules.

0 / 1 : Normal / Power-down

6-13. Internal High RC oscillator control Register (ihrcr), IO address = 0x0b

Bit

Reset

R/W

Description

7 – 0

Bit [7:0] for frequency calibration of IHRC.

This register is for system using only, please do NOT write this register.

6-14. Interrupt Edge Select Register (integs), IO address = 0x0c

Bit

Reset

R/W

Description

7 – 5

Reserved.

Timer16 edge selection.

0 : rising edge of the selected bit to trigger interrupt

1 : falling edge of the selected bit to trigger interrupt

3 – 2

PB0 or PB7 interrupt edge selection.

00 : both rising edge and falling edge of the selected bit to trigger interrupt

01 : rising edge of the selected bit to trigger interrupt

10 : falling edge of the selected bit to trigger interrupt

11 : reserved.

Note: If rop.0=0, PB0 is selected; If rop.0=1, PB7 is selected.

1 – 0

PA0 or PA5 interrupt edge selection.

00 : both rising edge and falling edge of the selected bit to trigger interrupt

01 : rising edge of the selected bit to trigger interrupt

10 : falling edge of the selected bit to trigger interrupt

11 : reserved.

Note: If rop.1=0, PA0 is selected; If rop.1=1, PA5 is selected.

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