LMK04832PAPSLASHEM datasheet(28/102 Pages) TI

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8.3.3.2.3 SYSREF Request

This mode allows an external source to synchronously turn on or off a continuous stream of SYSREF pulses

using the SYNC/SYSREF_REQ pin.

Setup the mode by programming SYSREF_REQ_EN = 1 and SYSREF_MUX = 2 (Pulser). The pulser does not

need to be powered for this mode of operation.

When the SYSREF_REQ pin is asserted, the SYSREF_MUX is synchronously set to continuous mode,

providing continuous pulses at the SYSREF frequency until the SYSREF_REQ pin is unasserted. When the

SYSREF_REQ pin is unasserted, the final SYSREF pulse completes sending synchronously.

8.3.4 Digital Delay

Digital (coarse) delay allows a group of outputs to be delayed by 8 to 1023 clock distribution path cycles. The

delay step can be as small as half the period of the clock distribution path cycle by using the DCLKX_Y_HS bit.

There are two different ways to use the digital delay:

1. Fixed digital delay

2. Dynamic digital delay

In both delay modes, the regular clock divider is substituted with an alternative divide value.

8.3.4.1 Fixed Digital Delay

Fixed digital delay value takes effect on the clock outputs after a SYNC event. As such, the outputs will be LOW

for a while during the SYNC event. Applications that cannot accept clock breakup when adjusting digital delay

during application run time should use dynamic digital delay to adjust phase.

8.3.4.1.1 Fixed Digital Delay Example

Assuming the device already has the following initial configurations and the application delays CLKOUT2 by one

VCO cycle compared to CLKOUT0:

• VCO frequency = 2949.12 MHz

• CLKOUT0 = 368.64 MHz (DCLK0_1_DIV = 8, CLKOUT0_SRC_MUX = 0 (Device Clock))

• CLKOUT2 = 368.64 MHz (DCLK2_3_DIV = 8, CLKOUT2_SRC_MUX = 0 (Device Clock))

The following steps should be followed:

1. Set DCLK0_1_DDLY = 8 and DCLK2_3_DDLY = 9. Static delay for each clock.

2. Set DCLK0_1_DDLY_PD = 0 and DCLK2_3_DDLY_PD = 0. Power up the digital delay circuit.

3. Set SYNC_DIS0 = 0 and SYNC_DIS2 = 0. Allow the outputs to be synchronized.

4. Perform SYNC by asserting, then unasserting SYNC. The can be done by either using the SYNC_POL bit or

the SYNC pin.

5. Now that the SYNC is complete, you can power down DCLK0_1_DDLY_PD = 1 and/or DCLK2_3_DDLY_PD

= 1 to save power.

6. Set SYNC_DIS0 = 1 and SYNC_DIS2 = 1. Prevent the output from being synchronized, as this is very

important for steady-state operation when using JESD204B/C.

CLKout0

368.64 MHz

CLKout2

368.64 MHz

No CLKout during SYNC

SYNC event

1 VCO cycle delay

Figure 8-4. Fixed Digital Delay Example

LMK04832-SEP

SNAS838A – OCTOBER 2022 – REVISED NOVEMBER 2022

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