LMK04832PAPSLASHEM datasheet(49/102 Pages) TI

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8.6.2.2.6 SCLKX_Y_ADLY_EN, SCLKX_Y_ADLY

These registers set the analog delay parameters for the SYSREF outputs.

Table 8-24. Registers 0x105, 0x10D, 0x115, 0x11D, 0x125, 0x12D, 0x135

BIT

NAME

POR DEFAULT

DESCRIPTION

7:6

Reserved

SCLKX_Y

_ADLY_EN

Enables analog delay for the SYSREF output.

0: Disabled

1: Enabled

4:0

SCLKX_Y

_ADLY

SYSREF analog delay in approximately 21 ps steps. Selecting analog delay

adds an additional 125 ps in propagation delay. Range is 125 ps to 608 ps.

Field Value

Delay Value

0 (0x0)

125 ps

1 (0x1)

146 ps (+21 ps from 0x00)

2 (0x2)

167 ps (+42 ps from 0x00)

3 (0x3)

188 ps (+63 ps from 0x00)

...

14 (0xE)

587 ps (+462 ps from 0x00)

15 (0xF)

608 ps (+483 ps from 0x00)

8.6.2.2.7 SCLKX_Y_DDLY

Table 8-25. Registers 0x106, 0x10E, 0x116, 0x11E, 0x126, 0x12E, 0x136

BIT

NAME

POR DEFAULT

DESCRIPTION

7:4

Reserved

3:0

SCLKX_Y_DDLY

Sets the number of VCO cycles to delay SDCLKout by

Field Value

Delay Cycles

0 (0x00)

Bypass

1 (0x01)

2 (0x02)

...

10 (0x0A)

11 to 15 (0x0B to 0x0F)

Reserved

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LMK04832-SEP

SNAS838A – OCTOBER 2022 – REVISED NOVEMBER 2022

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