LMK04832PAPSLASHEM datasheet(48/102 Pages) TI

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8.6.2.2.5 CLKoutY_SRC_MUX, SCLKX_Y_PD, SCLKX_Y_DIS_MODE, SCLKX_Y_POL, SCLKX_Y_HS

These registers set the half step for the device clock, the SYSREF output MUX, the SYSREF clock digital delay,

and half step.

Table 8-23. Registers 0x104, 0x10C, 0x114, 0x11C, 0x124, 0x12C, 0x134

BIT

NAME

POR DEFAULT

DESCRIPTION

7:6

Reserved

CLKoutY_SRC_MUX

Select CLKoutX clock source. Source must also be powered up.

0: Device Clock

1: SYSREF

SCLKX_Y_PD

Power down the SYSREF clock output circuitry.

0: SYSREF enabled

1: Power down SYSREF path for clock pair.

3:2

SCLKX_Y_DIS_MODE

Set disable mode for clock outputs controlled by SYSREF. Some cases will

assert when SYSREF_GBL_PD = 1.

Field Value

Disable Mode

0 (0x00)

Active in normal operation

1 (0x01)

If SYSREF_GBL_PD = 1, the output is

a logic low, otherwise it is active.

2 (0x02)

If SYSREF_GBL_PD = 1, the output is

a nominal Vcm voltage for odd clock

channels(1) and low for even clocks.

Otherwise outputs are active.

3 (0x03)

Output is a nominal Vcm voltage(1)

SCLKX_Y_POL

Sets the polarity of clock on SCLKX_Y when SYSREF clock output is selected

with CLKoutX_MUX or CLKoutY_MUX.

0: Normal

1: Inverted

SCLKX_Y_HS

Sets the local SYSREF clock half step value.

0: No phase adjustment

1: Adjust device SYSREF phase -0.5 clock distribution path cycles.

(1)

If LVPECL mode is used with emitter resistors to ground, the output Vcm will be approximately 0 V, each pin will be approximately 0 V.

If CML mode is used with pullups to VCC, the output VCM will be approximately VCC V, each pin will be approximately VCC V.

LMK04832-SEP

SNAS838A – OCTOBER 2022 – REVISED NOVEMBER 2022

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