LMK04832PAPSLASHEM datasheet(47/102 Pages) TI

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8.6.2.2.4 CLKoutX_SRC_MUX, DCLKX_Y_PD, DCLKX_Y_BYP, DCLKX_Y_DCC, DCLKX_Y_POL, DCLKX_Y_HS

These registers control the analog delay properties for the device clocks.

Table 8-22. Registers 0x103, 0x10B, 0x113, 0x11B, 0x123, 0x12B, 0x133

BIT

NAME

POR DEFAULT

DESCRIPTION

Reserved

CLKoutX_SRC_MUX

Select CLKoutX clock source. Source must also be powered up.

0: Device Clock

1: SYSREF

DCLKX_Y_PD

Power down the clock group defined by X and Y.

0: Enabled

1: Power down enter clock group X_Y.

DCLKX_BYP

Enable high performance bypass path for even clock outputs.

0: CLKoutX not in high performance bypass mode. CML is not valid for

CLKoutX_FMT.

1: CLKoutX in high performance bypass mode. Only CML clock format is valid.

DCLKX_Y_DCC

Duty cycle correction for device clock divider. Required for half step.

0: No duty cycle correction.

1: Duty cycle correction enabled.

DCLKX_Y_POL

Invert polarity of device clock output. This also applies to CLKoutX in high

performance bypass mode. Polarity invert is a method to get a half-step phase

adjustment in high performance bypass mode or /1 divide value.

0: Normal polarity

1: Invert polarity

DCLKX_Y_HS

Sets the device clock half step value. Must be set to zero (0) for a divide of 1.

No effect if DCLKX_Y_DCC = 0.

0: No phase adjustment

1: Adjust device clock phase –0.5 clock distribution path cycles.

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LMK04832-SEP

SNAS838A – OCTOBER 2022 – REVISED NOVEMBER 2022

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LMK04832PAP/EM Datasheet(PDF) 47 Page - Texas Instruments