LMK04832PAPSLASHEM datasheet(68/102 Pages) TI

68 / 102 page

8.6.2.6.6 CLKin_OVERRIDE, HOLDOVER_EXIT_MODE, HOLDOVER_PLL1_DET, LOS_EXTERNAL_INPUT,

HOLDOVER_VTUNE_DET, CLKin_SWITCH_CP_TRI, HOLDOVER_EN

This register has controls for enabling clock in switch events.

Table 8-52. Register 0x150

BIT

NAME

POR DEFAULT

DESCRIPTION

Reserved

CLKin

_OVERRIDE

When manual clock select is enabled, then CLKin_SEL_MANUAL = 0/1/2

selects a manual clock input. CLKin_OVERRIDE = 1 will force that clock

input. CLKin_OVERRIDE = 1 is used with clock distribution mode for best

performance.

0: Normal, no override.

1: Force select of only CLKin0/1/2 as specified by CLKin_SEL_MANUAL in

manual mode. Dynamic digital delay will not operate.

HOLDOVER_

EXIT_MODE

0: Exit based on LOS status. If clock is active by LOS, then begin exit.

1: Exit based on PLL1 DLD. When the PLL1 phase detector confirming valid

clock.

HOLDOVER

_PLL1_DET

This enables the HOLDOVER when PLL1 lock detect signal transitions from

high to low.

0: PLL1 DLD does not cause a clock switch event

1: PLL1 DLD causes a clock switch event

LOS_EXTERNAL_INPUT

Use external signals for LOS status instead of internal LOS circuitry.

CLKin_SEL0 pin is used for CLKin0 LOS, CLKin_SEL1 pin is used for CLKin1

LOS, and Status_LD1 is used for CLKin2 LOS. For any of these pins to be

valid, the corresponding _TYPE register must be programmed as an input.

0: Disabled

1: Enabled

HOLDOVER_

VTUNE_DET

Enables the DAC Vtune rail detector. When the DAC achieves a specified

Vtune, if this bit is enabled, the current clock input is considered invalid and an

input clock switch event is generated.

0: Disabled

1: Enabled

CLKin_SWITCH_CP_TRI

Enable clock switching with tri-stated charge pump.

0: Not enabled.

1: PLL1 charge pump tri-states during clock switching.

HOLDOVER_EN

Sets whether holdover mode is active or not.

0: Disabled

1: Enabled

LMK04832-SEP

SNAS838A – OCTOBER 2022 – REVISED NOVEMBER 2022

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