LMK04832PAPSLASHEM datasheet(19/102 Pages) TI

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Each clock output pair includes a local SYSREF analog and digital delay for unique phase adjustment of each

SYSREF clock.

The local analog delay allows for approximately 21-ps steps. Turning-on analog delay adds an additional 124 ps

of delay in the clock path. The digital delay step can be as small as half the period of the clock distribution path.

For example, a 3.2-GHz VCO frequency results in 156.25-ps steps.

The local digital delay and half step allows a SYSREF output to be delayed from 1.5 to 11 clock distribution path

cycles.

8.1.5.7 Programmable Output Formats

All clock outputs can be programmed to an LVDS, HSDS, LVPECL, or LCPECL output type. Odd clock outputs

in addition to CLKOUT8 and CLKOUT10 may also be programmed to LVCMOS. All odd clock outputs can also

be programmed to CML. When in bypass mode the even clock output may only be CML.

The OSCout can be programmed to an LVDS, LVPECL, or LVCMOS output type.

Any HSDS output type can be programmed to 6-mA or 8-mA amplitude levels.

Any LVPECL output type can be programmed to 1600-mVpp or 2000-mVpp amplitude levels. The 2000-mVpp

LVPECL output type is a Texas Instruments proprietary configuration that produces a 2000-mVpp differential

swing for compatibility with many data converters and is also known as 2VPECL.

LCPECL allows for DC-coupling SYSREF to low voltage JESD204B/C targets.

8.1.5.8 Clock Output Synchronization

Using the SYNC input causes all active clock outputs to share a rising edge as programmed by fixed digital

delay.

The SYNC event must occur for digital delay values to take effect.

8.1.6 0-Delay

Two types of 0-delay mode are supported.

1. Cascaded 0-delay

2. Nested 0-delay

Cascaded 0-delay mode establishes a fixed deterministic phase relationship of the phase of the PLL2 input

clock (OSCIN) to the phase of a clock output selected by the feedback mux. The 0-delay feedback uses

internal feedback from the CLKOUT6, CLKOUT8, or SYSREF. The 0-delay feedback can also be from an

external feedback through the FBCLKIN pins. The FB_MUX selects the feedback source. The OSCIN has a

fixed deterministic phase relationship to the feedback clock, therefore OSCout will also have a fixed deterministic

phase relationship to the feedback clock. In this mode, PLL1 input clock (CLKINx) also has a fixed deterministic

phase relationship to PLL2 input clock (OSCIN); this results in a fixed deterministic phase relationship between

all clocks from CLKINx to the clock outputs.

Nested 0-delay mode establishes a fixed deterministic phase relationship of the phase of the PLL1 input clock

(CLKINx) to the phase of a clock output selected by the feedback mux. The 0-delay feedback uses internal

feedback from the CLKOUT6, CLKOUT8, or SYSREF. The 0-delay feedback can also be from an external

feedback through the FBCLKIN port. The FB_MUX selects the feedback source.

Without using 0-delay mode, there will be n possible fixed phase relationships from clock input to clock output

depending on the clock output divide value.

Using an external 0-delay feedback reduces the number of available clock inputs by one.

8.1.7 Status Pins

The status pins can be monitored for feedback or in some cases used for input depending upon device

programming. For example:

• The CLKin_SEL0 pin may indicate the LOS (loss-of-signal) for CLKIN0.

• The CLKin_SEL1 pin may be an input for selecting the active clock input.

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LMK04832-SEP

SNAS838A – OCTOBER 2022 – REVISED NOVEMBER 2022

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