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LMK04832PAP/EM Datasheet(PDF) 69 Page - Texas Instruments |
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LMK04832PAP/EM Datasheet(HTML) 69 Page - Texas Instruments |
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69 / 102 page  8.6.2.6.7 HOLDOVER_DLD_CNT Table 8-53. HOLDOVER_DLD_CNT[13:0] MSB LSB 0x151[5:0] / HOLDOVER_DLD_CNT[13:8] 0x152[7:0] / HOLDOVER_DLD_CNT[7:0] This register has the number of valid clocks of PLL1 PDF before holdover is exited. Table 8-54. Registers 0x151 and 0x152 REGISTER BIT NAME POR DEFAULT DESCRIPTION 0x151 7:6 NA 0 Reserved 0x151 5:0 HOLDOVER _DLD_CNT[13:8] 2 The number of valid clocks of PLL1 PDF before holdover mode is exited. Field Value Count Value 0 (0x00) 0 1 (0x01) 1 0x152 7:0 HOLDOVER _DLD_CNT[7:0] 0 2 (0x02) 2 ... ... 16382 (0x3FFE) 16382 16383 (0x3FFF) 16383 www.ti.com LMK04832-SEP SNAS838A – OCTOBER 2022 – REVISED NOVEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 69 Product Folder Links: LMK04832-SEP |
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