LMK04832PAPSLASHEM datasheet(45/102 Pages) TI

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8.6.2.2.2 DCLKX_Y_DDLY

This register controls the digital delay for the device clock outputs.

Table 8-17. DCLKX_Y_DDLY Field Registers

MSB

LSB

0x0102[2:3] = DCLK0_1_DDLY[9:8]

0x101[7:0] = DCLK0_1_DDLY[7:0]

0x010A[2:3] = DCLK2_3_DDLY[9:8]

0x109[7:0] = DCLK2_3_DDLY[7:0]

0x0112[2:3] = DCLK4_5_DDLY[9:8]

0x111[7:0] = DCLK4_5_DDLY[7:0]

0x011A[2:3] = DCLK6_7_DDLY[9:8]

0x119[7:0] = DCLK6_7_DDLY[7:0]

0x0122[2:3] = DCLK8_9_DDLY[9:8]

0x121[7:0] = DCLK8_9_DDLY[7:0]

0x012A[2:3] = DCLK10_11_DDLY[9:8]

0x129[7:0] = DCLK10_11_DDLY[7:0]

0x0132[2:3] = DCLK12_13_DDLY[9:8]

0x131[7:0] = DCLK12_13_DDLY[7:0]

Table 8-18. Registers 0x101, 0x109, 0x111, 0x119, 0x121, 0x129, 0x131

0x102, 0x10A, 0x112, 0x11A, 0x122, 0x12A, 0x132

BIT

NAME

POR DEFAULT

DESCRIPTION

0x102,

0x10A,

0x112,

0x11A,

0x122,

0x12A, 0x132

2:3

DCLKX_Y_DDLY[9:8]

10 (0x0A)

Static digital delay which takes effect after a SYNC.

0x101,

0x109, 0x111,

0x119,

0x121,

0x129, 0x131

7:0

DCLKX_Y_DDLY[7:0]

Field Value

Delay Values

0 (0x00)

Reserved

1 (0x01)

Reserved

...

7 (0x07)

Reserved

8 (0x08)

9 (0x09)

...

1022 (0x3FE)

1022

1023 (0x3FF)

1023

Depending on the DCLK divide value, there may be an adjustment in phase delay required. Table 8-19 illustrate

the impact of different divide values on the final digital delay.

Table 8-19. Digital Delay Adjustment based on Divide Values

DIVIDE VALUE

DIGITAL DELAY ADJUSTMENT

2, 3

–2(1)

4, 7 to 1023

(1)

Before SYNC, program divider to Divide-by-4, then back to Divide-by-2 or Divide-by-3 to ensure '-2' delay relationship.

For example, Table 8-20 shows a system with clock outputs having divide values /2,/4,/5 and /6 to share a

common edge.

Table 8-20. Digital Delay Adjustment Illustration

DIVIDE VALUE

PROGRAMMED DDLY

ACTUAL DDLY

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LMK04832-SEP

SNAS838A – OCTOBER 2022 – REVISED NOVEMBER 2022

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