LMK04832PAPSLASHEM datasheet(85/102 Pages) TI

85 / 102 page

Table 9-3. Crosstalk Matrix

CLK0,CLK1

CLK2,CLK3

CLK4,CLK5

CLK6,CLK7

CLK8,CLK9

CLK10,CLK11

CLK12,CLK13

CLK0,

CLK1

n/a

CLK2,

CLK3

n/a

CLK4,

CLK5

n/a

CLK6,

CLK7

n/a

CLK8,

CLK9

n/a

CLK10,

CLK11

n/a

CLK12,

CLK13

n/a

L = Low Crosstalk, M = Medium Crosstalk, H = High Crosstalk

9.1.3 Digital Lock Detect Frequency Accuracy

The digital lock detect circuit is used to determine PLL1 locked, PLL2 locked, and holdover exit events. A

window size and lock count register are programmed to set a ppm frequency accuracy of reference to feedback

signals of the PLL for each event to occur. When a PLL digital lock event occurs, the digital lock detect

of the PLL is asserted true. When the holdover exit event occurs, the device will exit holdover mode when

HOLDOVER_EXIT_MODE = 1 (Exit based on DLD).

Table 9-4. Digital Lock Detect Related Fields

EVENT

PLL

WINDOW SIZE

LOCK COUNT

PLL1 Locked

PLL1

PLL1_WND_SIZE

PLL1_DLD_CNT

PLL2 Locked

PLL2

PLL2_WND_SIZE

PLL2_DLD_CNT

Holdover exit

PLL1

PLL1_WND_SIZE

HOLDOVER_DLD_CNT

For a digital lock detect event to occur, there must be a lock count number of phase detector cycles of PLLX

during which the time and phase error of the PLLX_R reference and PLLX_N feedback signal edges are within

the user programmable window size. There must be at least one lock count phase detector event before a lock

event occurs, therefore a minimum digital lock event time can be calculated as lock count / fPDX where X = 1 for

PLL1 or 2 for PLL2.

By using Equation 4, values for a lock count and window size can be chosen to set the frequency accuracy

required by the system in ppm before the digital lock detect event occurs:

1e6 × PLLX_WND_SIZE × fPDX

PLLX_DLD_CNT

ppm =

(4)

The effect of the lock count value is that it shortens the effective lock window size by dividing the window size by

lock count.

If at any time the PLLX_R reference and PLLX_N feedback signals are outside the time window set by window

size, then the lock count value is reset to 0.

9.1.3.1 Minimum Lock Time Calculation Example

To calculate the minimum PLL2 digital lock time given a PLL2 phase detector frequency of 40 MHz and

PLL2_DLD_CNT = 10,000. Then, the minimum lock time of PLL2 will be 10,000 / 40 MHz = 250 µs.

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LMK04832-SEP

SNAS838A – OCTOBER 2022 – REVISED NOVEMBER 2022

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