LMK04832PAPSLASHEM datasheet(13/102 Pages) TI

Part #	LMK04832PAP/EM

Description	LMK04832-SEP Space Grade Ultra-Low-Noise JESD204B/C Dual-Loop Clock Jitter Cleaner

PDF	102 Pages

Scroll/Zoom	100%

Manufacturer	TI [Texas Instruments]

Direct Link	http://www.ti.com

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13 / 102 page

6.8 Typical Characteristics

Jitter from 100 Hz to 100 MHz = 63.6 fs rms.

Output is CLKOUT4 as CML 32 mA with 68-nH to 20-Ω DC

bias.

Other settings are CLKout4_5_IDL = 1

and CLKout4_5_BYP = 1.

PLL2 Loop Filter R2 = 470 Ω, C2 = 150 nF,

Charge Pump = 3200 µA.

Reference is R&S SMA100B Signal Generator with option

SMAB - B711 through Prodyn BIB-100G Balun to OSCin.

Figure 6-2. PLL2 With VCO1 Performance at

2500 MHz With 312.5-MHz OSCin/Phase Detector

Frequency

Jitter from 100 Hz to 100 MHz = 67 fs rms.

Output is CLKOUT4 as CML 32 mA with 68-nH to 20-Ω DC

bias.

Other settings are CLKout4_5_IDL = 1

and CLKout4_5_BYP = 1.

PLL2 Loop Filter R2 = 470 Ω, C2 = 150 nF,

Charge Pump = 3200 µA.

Reference is R&S SMA100B Signal Generator with option

SMAB - B711 through Prodyn BIB-100G Balun to OSCin.

Figure 6-3. PLL2 With VCO1 Performance at

3200 MHz With 320-MHz OSCin/Phase Detector

Frequency

www.ti.com

LMK04832-SEP

SNAS838A – OCTOBER 2022 – REVISED NOVEMBER 2022

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LMK04832PAP/EM Datasheet(PDF) 13 Page - Texas Instruments