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LMK04832PAP/EM Datasheet(PDF) 73 Page - Texas Instruments

Part # LMK04832PAP/EM
Description  LMK04832-SEP Space Grade Ultra-Low-Noise JESD204B/C Dual-Loop Clock Jitter Cleaner
PDF  102 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

LMK04832PAP/EM Datasheet(HTML) 73 Page - Texas Instruments

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8.6.2.7.6 PLL1_DLD_CNT
Table 8-64. PLL1_DLD_CNT[13:0]
MSB
LSB
0x15C[5:0] / PLL1_DLD_CNT[13:8]
0x15D[7:0] / PLL1_DLD_CNT[7:0]
This register contains the value of the PLL1 DLD counter.
Table 8-65. Registers 0x15C and 0x15D
REGISTER
BIT
NAME
POR DEFAULT
DESCRIPTION
0x15C
7:6
NA
0
Reserved
0x15C
5:0
PLL1_DLD
_CNT[13:8]
32
The reference and feedback of PLL1 must be within the
window of phase error as specified by PLL1_WND_SIZE for
this many phase detector cycles before PLL1 digital lock
detect is asserted.
Field Value
Delay Value
0 (0x00)
Reserved
1 (0x01)
1
0x15D
7:0
PLL1_DLD
_CNT[7:0]
0
2 (0x02)
2
3 (0x03)
3
...
...
16,382 (0x3FFE)
16,382
16,383 (0x3FFF)
16,383
8.6.2.7.7 HOLDOVER_EXIT_NADJ
Table 8-66. Register 0x15E
BIT
NAME
POR DEFAULT
DESCRIPTION
7:5
NA
0
Reserved
4:0
HOLDOVER_EXIT_NADJ
30
When holdover exists, PLL1 R counter and PLL1 N
counter are reset. HOLDOVER_EXIT_NADJ is a 2s
complement number which provides a relative timing
offset between PLL1 R and PLL1 N divider.
www.ti.com
LMK04832-SEP
SNAS838A – OCTOBER 2022 – REVISED NOVEMBER 2022
Copyright © 2022 Texas Instruments Incorporated
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Product Folder Links: LMK04832-SEP



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