LMK04832PAPSLASHEM datasheet(56/102 Pages) TI

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8.6.2.3.7 PLL1_PD, VCO_LDO_PD, VCO_PD, OSCin_PD, SYSREF_GBL_PD, SYSREF_PD, SYSREF_DDLY_PD,

SYSREF_PLSR_PD

This register contains power-down controls for OSCIN and SYSREF functions.

Table 8-36. Register 0x140

BIT

NAME

POR DEFAULT

DESCRIPTION

PLL1_PD

Power down PLL1

0: Normal operation

1: Power down

VCO_LDO_PD

Power down VCO_LDO

0: Normal operation

1: Power down

VCO_PD

Power down VCO

0: Normal operation

1: Power down

OSCin_PD

Power down the OSCIN port.

0: Normal operation

1: Power down

SYSREF_GBL_PD

Power down individual SYSREF outputs depending on the setting of

SCLKX_Y_DIS_MODE for each SYSREF output. SYSREF_GBL_PD allows

many SYSREF outputs to be controlled through a single bit.

0: Normal operation

1: Activate Power down Mode

SYSREF_PD

Power down the SYSREF circuitry and divider. If powered down, SYSREF

output mode cannot be used. SYNC cannot be provided either.

0: SYSREF can be used as programmed by individual SYSREF output

registers.

1: Power down

SYSREF_DDLY_PD

Power down the SYSREF digital delay circuitry.

0: Normal operation, SYSREF digital delay may be used. Must be powered up

during SYNC for deterministic phase relationship with other clocks.

1: Power down

SYSREF_PLSR_PD

Power down the SYSREF pulse generator.

0: Normal operation

1: Power down

LMK04832-SEP

SNAS838A – OCTOBER 2022 – REVISED NOVEMBER 2022

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LMK04832PAP/EM Datasheet(PDF) 56 Page - Texas Instruments

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