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LMK04832PAP/EM Datasheet(PDF) 39 Page - Texas Instruments |
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LMK04832PAP/EM Datasheet(HTML) 39 Page - Texas Instruments |
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39 / 102 page  Table 8-6. Register Map (continued) ADDRESS [14:0] DATA[7:0] 23:8 7 6 5 4 3 2 1 0 0x11A CLKout6_7_PD CLKout6_7_OD L CLKout6_7_IDL DCLK6_7_DDLY _PD DCLK6_7_DDLY[9:8] DCLK6_7_DIV[9:8] 0x11B 0 1 CLKout6_SRC_ MUX DCLK6_7_PD DCLK6_7_BYP DCLK6_7_DCC DCLK6_7_POL DCLK6_7_HS 0x11C 0 0 CLKout7_SRC_ MUX SCLK6_7_PD SCLK6_7_DIS_MODE SCLK6_7_POL SCLK6_7_HS 0x11D 0 0 SCLK6_7_ADLY _EN SCLK6_7_ADLY 0x11E 0 0 0 0 SCLK6_7_DDLY 0x11F CLKout7_FMT CLKout6_FMT 0x120 DCLK8_9_DIV[7:0] 0x121 DCLK8_9_DDLY[7:0] 0x122 CLKout8_9_PD CLKout8_9_OD L CLKout8_9_IDL DCLK8_9_DDLY _PD DCLK8_9_DDLY[9:8] DCLK8_9_DIV[9:8] 0x123 0 1 CLKout8_SRC_ MUX DCLK8_9_PD DCLK8_9_BYP DCLK8_9_DCC DCLK8_9_POL DCLK8_9_HS 0x124 0 0 CLKout9_SRC_ MUX SCLK8_9_PD SCLK8_9_DIS_MODE SCLK8_9_POL SCLK8_9_HS 0x125 0 0 SCLK8_9_ADLY _EN SCLK8_9_ADLY 0x126 0 0 0 0 SCLK8_9_DDLY 0x127 CLKout9_FMT CLKout8_FMT 0x128 DCLK10_11_DIV[7:0] 0x129 DCLK10_11_DDLY[7:0] 0x12A CLKout10_11_P D CLKout10_11_O DL CLKout10_11_I DL DCLK10_11_DD LY_PD DCLK10_11_DDLY[9:8] DCLK10_11_DIV[9:8] 0x12B 0 1 CLKout10_SRC _MUX DCLK10_11_PD DCLK10_11_BY P DCLK10_11_DC C DCLK10_11_PO L DCLK10_11_HS 0x12C 0 0 CLKout11_SRC _MUX SCLK10_11_PD SCLK10_11_DIS_MODE SCLK10_11_PO L SCLK10_11_HS 0x12D 0 0 SCLK10_11_AD LY_EN SCLK10_11_ADLY 0x12E 0 0 0 0 SCLK10_11_DDLY 0x12F CLKout11_FMT CLKout10_FMT 0x130 DCLK12_13_DIV[7:0] 0x131 DCLK12_13_DDLY[7:0] 0x132 CLKout12_13_P D CLKout12_13_O DL CLKout12_13_I DL DCLK12_13_DD LY_PD DCLK12_13_DDLY[9:8] DCLK12_13_DIV[9:8] 0x133 0 1 CLKout12_SRC _MUX DCLK12_13_PD DCLK12_13_BY P DCLK12_13_DC C DCLK12_13_PO L DCLK12_13_HS 0x134 0 0 CLKout13_SRC _MUX SCLK12_13_PD SCLK12_13_DIS_MODE SCLK12_13_PO L SCLK12_13_HS 0x135 0 0 SCLK12_13_AD LY_EN SCLK12_13_ADLY 0x136 0 0 0 0 SCLK12_13_DDLY 0x137 CLKout13_FMT CLKout12_FMT 0x138 0 VCO_MUX OSCout_MUX OSCout_FMT 0x139 0 0 0 SYSREF_REQ_ EN SYNC_BYPASS 0 SYSREF_MUX 0x13A 0 0 0 SYSREF_DIV[12:8] 0x13B SYSREF_DIV[7:0] 0x13C 0 0 0 SYSREF_DDLY[12:8] 0x13D SYSREF_DDLY[7:0] 0x13E 0 0 0 0 0 SYSREF_PULSE_CNT www.ti.com LMK04832-SEP SNAS838A – OCTOBER 2022 – REVISED NOVEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 39 Product Folder Links: LMK04832-SEP |
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