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LMK04832PAP/EM Datasheet(PDF) 36 Page - Texas Instruments |
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LMK04832PAP/EM Datasheet(HTML) 36 Page - Texas Instruments |
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36 / 102 page  CLKINx_P CLKINx_N PLL1 Phase Detector/ Charge Pump R N Up to 3 inputs External Loop Filter N R PLL2 Phase Detector/ Charge Pump SYSREF Digital Delay Analog Delay Device Clock Divider Digital Delay PLL1 PLL2 External VCXO External Loop Filter OSCOUT_P OSCOUT_N CPOUT2 7 Blocks Global SYSREF Divider and Delay Device Clock Divider Digital Delay Device Clock Divider Digital Delay SYSREF Digital Delay Analog Delay SYSREF Digital Delay Analog Delay 7 Blocks Internal or external loopback, user programmable Up to 14 Clock or SYSREF Outputs CLKOUTx_P CLKOUTx_N CLKOUTy_P CLKOUTy_N Figure 8-12. Simplified Functional Block Diagram for Nested 0-Delay Dual Loop Mode 8.4.2 Single PLL 8.4.2.1 PLL2 Single Loop Figure 8-13 shows the use case of PLL2 single loop mode. When used with a high-frequency clean reference performance as good as dual loop mode may be achieved. Traditionally the OSCIN is used as a reference to PLL2, but it is also possible to use CLKINx as a reference to PLL2. N R PLL2 Phase Detector/ Charge Pump SYSREF Digital Delay Analog Delay Device Clock Divider Digital Delay PLL2 External Loop Filter OSCOUT_P OSCOUT_N CPOUT2 OSCIN_P 7 Blocks Global SYSREF Divider and Delay Device Clock Divider Digital Delay Device Clock Divider Digital Delay SYSREF Digital Delay Analog Delay SYSREF Digital Delay Analog Delay 7 Blocks OSCIN_N CLKINx_P CLKINx_N Up to 4 Inputs Up to 14 Clock or SYSREF Outputs CLKOUTx_P CLKOUTx_N CLKOUTy_P CLKOUTy_N Figure 8-13. Simplified Functional Block Diagram for Single Loop Mode 8.4.2.2 PLL2 With External VCO You can use the FIN0/FIN1 input pins to add an external VCO. The input may be single-ended or differential. At high frequency, the input impedance to FIN0/FIN1 is low. A resistive pad is recommended for matching. N R PLL2 Phase Detector/ Charge Pump SYSREF Digital Delay Analog Delay Device Clock Divider Digital Delay PLL2 External Loop Filter OSCOUT_P OSCOUT_N CPOUT2 OSCIN_P 7 Blocks Global SYSREF Divider and Delay Device Clock Divider Digital Delay Device Clock Divider Digital Delay SYSREF Digital Delay Analog Delay SYSREF Digital Delay Analog Delay 7 Blocks OSCIN_N CLKINx_P CLKINx_N Up to3 Inputs FIN0_P FIN0_N Up to 14 Clock or SYSREF Outputs CLKOUTx_P CLKOUTx_N CLKOUTy_P CLKOUTy_N Figure 8-14. Simplified Functional Block Diagram for Single Loop Mode With External VCO LMK04832-SEP SNAS838A – OCTOBER 2022 – REVISED NOVEMBER 2022 www.ti.com 36 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: LMK04832-SEP |
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