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LMK04832PAP/EM Datasheet(PDF) 12 Page - Texas Instruments |
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LMK04832PAP/EM Datasheet(HTML) 12 Page - Texas Instruments |
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12 / 102 page  6.6 Timing Requirements VDD, VDD_A = 3.3 V ± 5 %, –55 °C ≤TA ≤ 125 °C. Typical values are at VDD = VDD_A = 3.3 V, 25 °C (unless otherwise noted) SYMBOL PARAMETER MIN NOM MAX UNIT Timing Requirements tdS Setup time for SDI edge to SCK rising edge 40 ns tdH Hold time for SDI edge to SCK rising edge 20 ns tSCK Period of SCK 400 ns tHIGH High width of SCK 120 ns tLOW Low width of SCK 120 ns tCS Setup time for CS# falling edge to SCK rising edge 40 ns tCH Hold time for CS# rising edge from SCK rising edge 40 ns tDV SCK falling edge to valid read back data 120 ns 6.7 Timing Diagram Register programming information on the SDIO pin is clocked into a shift register on each rising edge of the SCK signal. On the rising edge of the CS* signal, the register is sent from the shift register to the register addressed. A slew rate of at least 30 V/µs is recommended for these signals. After programming is complete the CS* signal should be returned to a high state. If the SCK or SDIO lines are toggled while the VCO is in lock, as is sometimes the case when these lines are shared with other parts, the phase noise may be degraded during this programming. 4-wire mode read back has same timing as SDIO pin. R/W bit = 0 is for SPI write. R/W bit = 1 is for SPI read. SDIO (WRITE) SCK CS* tc H tc S td S t SC K t H IGH t LOW td H SDIO (Read) R/W A14 A13 D1 D0 D1 D0 td V A12 to A0, D7 to D2 D7 to D2 Figure 6-1. SPI Timing Diagram LMK04832-SEP SNAS838A – OCTOBER 2022 – REVISED NOVEMBER 2022 www.ti.com 12 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: LMK04832-SEP |
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