LMK04832PAPSLASHEM datasheet(17/102 Pages) TI

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8.1.2 Clock Inputs

Note

CLKIN1 can be used as a reference for dual loop, single loop, or clock distribution mode, providing

flexibility configuring the device for different operation modes from one clock input.

8.1.2.1 Inputs for PLL1

CLKIN0, CLKIN1, and CLKIN2 are the three redundant inputs with their own PLL1 R dividers that can be used

as a reference input to PLL1. The switching between these inputs can either be automatic or manual. For

manual switching, CLKIN_SEL0 and CLKIN_SEL1 pins can be used for faster speed. These input pins are also

shared for other functions.

• CLKIN1 is shared for use as an external 0-delay feedback (FBCLKIN), or for use with an external VCO (FIN).

• CLKIN2 is shared for use as OSCout. To use CLKIN2 as an input power down OSCout, see the VCO_MUX,

OSCout_MUX, OSCout_FMT section.

8.1.2.2 Inputs for PLL2

In dual loop configurations, the PLL2 reference is from OSCin. However, in single PLL2 loop operation, it is also

possible to use any of the three CLKIN inputs of PLL1 as a reference to PLL2.

8.1.2.3 Inputs When Using Clock Distribution Mode

For clock distribution mode, a reference signal may be applied to the FIN0 or FIN1 pins. CLKIN0 can be used

to distribute a SYSREF signal through the device. In this use case, CLKIN0 is re-clocked by CLKIN1. The FIN0

pins are generally recommended over the FIN1 pins because they allow higher frequency, use a lower noise

path, and cannot be used for other functions (like redundant input).

8.1.3 PLL1

PLL1 allows low offset jitter cleaning as well as the use of redundant inputs and frequency holdover.

8.1.3.1 Frequency Holdover

Frequency holdover keeps the clock outputs on frequency with minimum drift when the reference is lost until a

valid reference clock signal is re-established. This can only be used if PLL1 is used.

8.1.3.2 External VCXO for PLL1

When PLL1 is used, an external VCXO is required. The close-in noise performance of this VCXO is critical for

good jitter cleaning performance. The OSCout pin is powered on by default and gives a buffered copy of the

PLL1 feedback and PLL2 reference input at OSCin. This reference input is typically a low noise VCXO or XO.

This output can be used to clock external devices such as microcontrollers, FPGAs, CPLDs, and so forth, before

the device is programmed.

• The OSCout buffer output type is programmable to LVDS, LVPECL, or LVCMOS.

• The VCXO buffered output can be synchronized to the VCO clock distribution outputs by using Cascaded

0-Delay Mode.

8.1.4 PLL2

8.1.4.1 Internal VCOs for PLL2

PLL2 has two internal VCOs. The output of the selected VCO is routed to the Clock Distribution Path. This same

selection is also fed back to the PLL2 phase detector through a prescaler and N-divider.

8.1.4.2 External VCO Mode

An external VCO can be used with PLL2 with the input for the external VCO coming through FIN0 or FIN1,

although FIN0 is generally preferred.

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LMK04832-SEP

SNAS838A – OCTOBER 2022 – REVISED NOVEMBER 2022

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